Specific Process Knowledge/Lithography/EBL

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Electron-Beam Lithography at DTU Nanolab

DTU Nanolab has two EBL exposure systems, a JEOL JBX-9500FSZ and a Raith eLINE Plus system. The two systems are very different and new users should consult the EBL team to dertermine which system is appropriate for a particular project or type of sample. The general specifications of the two tools are given in the table below and may serve as a guideline for choice of system to use, especially the pros and cons list at the end of the table.

For more information and specific workflows on either tool, please refer to their respective pages; JEOL JBX-9500FSZ or Raith eLINE Plus.

Users can request training sessions on either of the two exposure systems by contacting e-beam@nanolab.dtu.dk. Please provide all relevant process information about your substrate/process in your inquiry.

EBL system comparison table
Equipment		JEOL JBX-9500FSZ	Raith eLINE Plus
Performance	Resolution	8 nm	35 nm
	Maximum writing field	1mm x 1mm	1mm x 1mm
Process parameter range	Acceleration voltage	100 kV	1-30 kV
	Scan speed	100 MHz	20 MHz
	Min. electron beam size	4 nm	10 nm
	Min. step size	0.25 nm	1 nm
	Beam current range	0.1 nA to 100 nA	0.01 to 12 nA
	Minimum dwell time	10 ns	50 ns
Samples	Batch size	Wafer cassettes: 6 x 2" wafers 2 x 4" wafers 1 x 6" wafer 1 x 8" wafer Special chip cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D).	Chips up to 75 x 75 mm 4" wafer holder 6" wafer holder (stage movement limited to central 100 x 100 mm region)
	Substrate material allowed	Silicon, quartz, pyrex, III-V materials Wafers with layers of silicon oxide or silicon (oxy)nitride Wafers with layers of metal	Silicon, quartz, pyrex, III-V materials Wafers with layers of silicon oxide or silicon (oxy)nitride Wafers with layers of metal
General considerations	Pros	100 kV Sub 10 nm resolution Automatic beam optimization High current and process speed Automatic sample exchange High level of programmability for automatic job execution EBL workhorse for large designs	Readily available More intuitive software Easier SEM mode alignment Build in SEM automation for post exposure process control 2D stacks (HBN/graphene) allowed without Al coating Excellent for small chips or small area design exposure
	Cons	Steep learning curve Availability - booking calendar is usually full 5 weeks ahead	Maximum 30 kV User dependent performance/beam optimization Minimum feature size >35 nm Difficult to handle design files >1 GB Slower writing speed

Generalized workflow

While the EBL workflow resembles that of UV lithography there are a few additional complications and the parameter space is somewhat larger. The complications all arise from using electrons rather than light for exposure. Since a beam of electrons is used for exposure the substrate must be sufficiently conductive and grounded in order not to build up a charge. If the substrate in itself is not conductive a thin metal film or other conductive surface layer must be applied to it, read more on this in the resist section. Another complication is secondary exposure from backscattered electrons. This is a much bigger topic and covered in the pattern preparation section. A generalised workflow is shown below.

Since substrate preparation and development processes are (nearly) identical for the JEOL and Raith eLine systems they are described in common below. Pattern preparation, job preparation and job execution are fairly different between the two tools and hence these steps are described on the specific tool pages.

Substrate preparation

Resist coating

An appropriate EBL resist must naturally be applied to the substrate. DTU Nanolab supplies a number of standard resists, please consult the table below. The default positive EBL resist is AR-P 6200.09 (CSAR). CSAR installed on Spin Coater: Gamma E-beam and UV for spin coating of 2", 4" and 6" substrates. For other substrate sizes (i.e. chips) or other resists Spin Coater: LabSpin 02/03 have to be used instead. The standard resist bottles are stored in the chemical cupboard in E-4.

Contrary to most UV resist it is in general not advisable to use HMDS priming when coating with EBL resists. There can of course be exceptions to this but we do not recommend HMDS priming when using the DTU Nanolab supplied EBL resists.

DTU Nanolab supplied standard EBL resists and process guides
Resist	Polarity	Manufacturer	Comments	Technical reports	Spin Coater	Thinner	Developer	Rinse	Remover	Process flows (in docx-format)
CSAR AR-P 6200	Positive	AllResist	Standard positive resist, very similar to ZEP520.	AR-P 6200 info	Spin Coater: Gamma E-beam and UV or Spin Coater: LabSpin 02/03	Anisole	AR-600-546 AR-600-548 N50 MIBK:IPA	IPA	AR-600-71 Remover 1165	CSAR CSAR with Al LOR5A with CSAR
Medusa AR-N 8200	Negative	AllResist	Both e-beam and DUV sensitive resist.	AR-N 8200 info	Spin Coater: LabSpin 02/03	AR 600-07	AR 300-47:DIW (1:1)	DIW	BOE
AR-N 7500	Negative	AllResist	Both e-beam, DUV and UV-sensitive resist.	AR-N 7500 info	Spin Coater: LabSpin 02/03	PGMEA	AR 300-47:DIW (4:1) MIF726:DIW (8:5)	DIW	AR 300-73 O2 plasma

It is possible to obtain permission to user other resists at DTU Nanolab, users must however provide these resists and possibly developers themselves. A non-exhaustive list of user supplied EBL resist used at DTU Nanolab and some process guidelines can be found in the table below.

Non standard, user supplied EBL resists and process guides
Resist	Polarity	Manufacturer	Comments	Technical reports	Spin Coater	Thinner	Developer	Rinse	Remover	Process flows (in docx-format)
ZEP520A	Positive resist, contact Lithography if you plan to use this resist	ZEON	Positive resist	ZEP520A.pdf, ZEP520A spin curves on SSE Spinner	See table here	Anisole	ZED-N50/Hexyl Acetate,n-amyl acetate, oxylene. JJAP-51-06FC05‎, JVB001037	IPA	acetone/1165	Process Flow ZEP
Copolymer AR-P 617	Positive	AllResist	Approved, not tested yet. Used for trilayer (PE-free) resist-stack or double-layer lift-off resist stack. Please contact Lithography for information.	AR_P617	See table here	PGME	AR 600-55, MIBK:IPA		acetone/1165	Trilayer stack: Process Flow
mr EBL 6000.1	Negative	MicroResist	Standard negative resist	mrEBL6000 processing Guidelines‎	See table here	Anisole	mr DEV	IPA	mr REM	Process Flow‎
HSQ (XR-1541)	Negative	DOW Corning	Approved. Standard negative resist	HSQ Dow Corning, MSDS HSQ	See table here		TMAH, AZ400K:H2O	H2O		process flow HSQ High resolution patterning with HSQ
AR-N 7520	Negative	AllResist	Both e-beam, DUV and UV-sensitive resist. Currently being tested, contact Peixiong Shi for information.	AR-N7500-7520	See table here	PGMEA	AR 300-47, TMAH	H2O
PMMA	Positive	AllResist			See table here	Anisole	MIBK:IPA (1:3), IPA:H2O	IPA	acetone/1165/Pirahna
ZEP7000	Positive	ZEON	Not approved. Low dose to clear, can be used for trilayer (PEC-free) resist-stack. Please contact Lithography for information.	ZEP7000.pdf	See table here	Anisole	ZED-500/Hexyl Acetate,n-amyl acetate, oxylene.	IPA	acetone/1165	Trilayer stack: Process Flow‎

Discharge layer application

As exposure is done with an electron beam, insulating substrates will cause a build up of charge that will deflect the incoming beam and disturb pattern definition. It is therefore necesarry when working with insulating substrates or substrates with thick (> 200 nm) dielectric films to apply a discharge layer. This is typically applied on top of the EBL resist layer and must be removed in between exposure and development. The most common discharge layer is 20 nm thermally evaporated Al. Bear in mind that it should be thermally evaporated and not e-beam evaporated. Thermal evaporation of Al can be done in Thermal evaporator and Wordentec. The Al layer can be removed with MIF726 after exposure. MIF726 etch rate in Al is about 0.5 nm/s, although only about 1 nm/min in oxidized aluminium.

For samples with 2D materials such as graphene, HBN, etc., it is mandatory to apply a 20 nm Al layer on top of the resist in order to expose the substrate in the JEOL 9500 system. The Raith eLine system does not have this requirement.

Another possibility is to use a spin-on conductive layer such as AR-PC 5090. It can be removed with water after exposure. At the moment we do not have much experience with this, contact the EBL team if you are interested in this option.

Inspection

Post exposure pattern dimensions are dependent on resist thickness. Thus, it is advisable to verify resist thickness after spin coating. This can be done by ellipsometry in the VASE Ellipsometer.

As the cleanliness requirement of the JEOL is very high, substrates that does not visually appear to be in a good condition will be rejected by the JEOL 9500 cassette loading team. It is therefore a good idea to perform your own visual inspection. The loading team will inspect your samples for any types of flakes or bubbles in the surface layers of the sample. Samples with flakes or bubbles will be rejected.

Samples with resist residues on the backside will also be rejected. If you do have resist residues on the backside of your wafer you should wipe it off with an appropriate solvent.

User resist bottles in the cleanroom

We recommend all groups or users to have their own bottle of e-beam resist inside the cleanroom. Please follow the guidelines below.

• Find a blue-capped glass bottle in the cupboard next to office 055 in 346 (outside the cleanroom).
• Bring the bottle inside gowning; clean it thoroughly on the outside with water or alcohol
• Bring the bottle to a fumehood inside the cleanroom; clean the bottle and the lid thoroughly on the inside with the main solvent of your resist, i.e. for CSAR use anisole. If in doubt which solvent your e-beam resist contains, consult the MSDS of the resist found here.
• If you need to dilute the resist, find a measurement beaker and clean it thoroughly in same solvent as your own bottle. For CSAR, ZEP, mr EBL, and anisole-based PMMA, you can use the measurement beaker in the box inside the fumehood in E-4.
• Let the bottle dry in the fumehood.
• Bring the (main) bottle of resist to the fumehood. Carefully unscrew the lid of the resist bottle. If necessary, wipe the thread of the resist bottle before you pour resist into your own bottle; dried resists may sit on the thread and be transferred into your bottle (or worse into the large resist bottle) when pouring.
• Clean all bottles on the outside with acetone or IPA, let them fume off in the fumehood. Clean the measurement beaker as well.
• Find a label to your resist bottle; bottles without labels will be removed from the cleanroom.
• Write name, Lotnumber, group and date on your bottle.

When spin coating e-beam resist, you should use a pipette to transfer resist from your bottle to the substrate. If you pour the resist directly from your bottle, you will leave resist in the thread that will soon dry out and leave particles in the resist. The disposable pipettes need to be thoroughly cleaned with a N2 gun before use (app. 20 s). After some practice, you can obtain particle-free 4" wafers if bottle and pipette (and spin coater) are properly cleaned.

Keep your resist bottles in up-right position, do not tilt or shake them too much, this can spread particles from the sidewall into the resist.

Development

AR 600-546 and ZED N-50 developers are available in a semi automatic puddle developer Developer E-beam in E-4, mainly intended for development of AR-P 6200 and ZEP 520A. It has automatic recipes for puddle development cycles for 10, 30 and 60 seconds of either of the two developers, each finishing off with an IPA rinse and drying cycle. The system can handle chips, 2", 4" and 6" wafers.

Other resist have to be developed in the E-beam developer fumehood in E-4 in beakers. Please notice there are specific beaker sets for alkaline developers and for solvent based developers.

Proximity Error Correction (PEC)

Example of dose modulated design file after Proximity Error Correction.

Even though the electron beam diameter is only a few nm, the feature and pitch resolution in resist is limited by scattering of the electrons in the resist and substrate material. Forward scattering is scattering within the resist layer and it will have a broadening effect of the beam. The magnitude of this effect depends on acceleration voltage, resist composition and thickness of the resist layer. Back scattering is caused by electron-matter interaction in the substrate itself and electrons that are scattered back into the resist layer will provide a secondary (unwanted) exposure of the resist. The scattering distance is highly dependent on acceleration voltage and the substrate material. For a silicon substrate exposed at 100 kV the back scatter range is up to 30 µm and hence it is essential for many designs to account for this effect using PEC software. At DTU Nanolab we primarily use Beamer from GenISys for PEC. The PEC process will result in a dose modulated design file where the relative exposure dose has been modulated to ensure that all parts of the design receives a uniform dose regardless of whether a design feature is in a sparsely populated or a heavily populated area of the design.

For more information on PEC and use of Beamer please refer to our dedicated Beamer & PEC page.

Charging of non-conductive substrates

Exposure on a non-conducting substrate the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist.

At DTU Nanolab, we recommend to use a thin (20 nm) layer of thermally evaporated aluminum on top of the e-beam resist. Preferably, the thickness of Al and the e-beam dose should be optimised to the features you wish to e-beam pattern [1]. A good starting point is 20 nm Al; from here dose and development can be optimised to reach the resolution and feature size required. The aluminum layer is easily removed with MIF726 after exposure and prior to development of the e-beam resist.

The process flow for a standard e-beam exposure on CSAR with Al on top can be found here Process Flow CSAR with Al.

If your process can not utilize a aluminum discharge layer, Espacer might be another possibility to pursue. Espacer is a chemical that works as a discharging layer; it is spun onto the wafer on top of the resist and easily rinsed off the wafer after e-beam exposure. Visit this page for more information: Espacer

Literature on E-beam Lithography

• Lithography, Wiley, 2011: Chapter 3, Electron Beam Lithography by Stefan Landis: http://onlinelibrary.wiley.com/doi/10.1002/9781118557662.ch3/summary

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Introduction to E-beam lithography at DTU Nanolab

DTU Nanolab has two E-beam writing systems, a JEOL JBX-9500 FSZ and a Raith eLINE Plus. Newcommers to EBL should start by watching our JEOL 9500 process video to see how a typical process is done. The Raith eLINE Plus is not operational yet, we expect to release it Q3 2022.

Compared to UV lithography EBL is somewhat more complicated and in general a significantly longer process. Writing time (per area) is much higher and thus EBL is only adviseable for structures with Critical Dimensions (CD) below 1 µm. For CD equal to or higher than 1 µm please consider our Maskless Aligner tools.

A typical EBL process will involve the following steps:

• Spin coating and soft baking of EBL resist
• Application of a discharge layer for non-conductive samples or samples with >200 nm insulating films
• Proximity Error Correction of design
• Splitting design into low current (fine detail) and high current (bulk) parts to reduce writing time
• Job file creation to define exposure parameters
• Sample mounting
• EBL calibration and beam optimization
• Exposure
• Discharge layer removal (if applied)
• Resist development

Guidelines and process information on all of these steps are available from links on this page.

A quick comparison table between our two EBL systems is provided below to help assess which tool is best suited for your process. Please contact our EBL staff if you have any questions regarding the two tools or which one is best suited for your process.

Equipment		JEOL JBX-9500FSZ	Raith eLINE Plus
Performance	Resolution	7 nm (HSQ)	8 nm
	Maximum writing area without stitching	1mm x 1mm	?
Process parameter range	E-beam voltage	100 kV	1-20 kV
	Scanning speed	100 MHz	?
	Min. electron beam size	4 nm	2 nm
	Min. step size	1 nm	?
	Beam current range	0.1nA to 60nA in normal conditions	?
	Dose range	0.001 - 100000µC/cm2	?
Samples	Batch size	Wafer cassettes: 6 x 2" wafers 3 x 4" wafers 2 x 4" wafers 1 x 6" wafer Chip cassette with slit openings of 20 mm, 12 mm, 8 mm and 4 mm	?
	Substrate material allowed	Any standard cleanroom material, except materials that will degas and special treatment for graphene	Any standard cleanroom material, except materials that will degas and special treatment for graphene

Training in E-Beam Lithography

Please request training in E-Beam lithography by sending an email with your process flow to e-beam@nanolab.dtu.dk.

Spin coating and resist information

Information on spin coating of EBL resist is available here.

Development

There are many different developers for different E-beam resist, but since CSAR and ZEP520A are the most used at Nanolab, we have installed a semi automatic puddle developer: Developer E-beam in E-4.

To accommodate most users, this tool uses developers: AR 600-546 for development of CSAR 6200 resist series and ZED N-50 for ZEP520A resists and IPA as a rinsing step. Intermediate results indicate that using ZED N-50 for CSAR 6200 series resist will introduce an elevated amount of residues, and vice verva for AR 600 - 546 used on ZEP 520A, but it is inconclusive.
We therefore recommend to use:

• ZED N-50 for Zep520A
• AR 600-546 for CSAR 6200 series

The recipes are divided into different developer and development times.

The recipes 546 are short for AR 600-546 and N-50 is short for ZED N-50.
After the developer there is a time indication eg. 10s, 30s, 60s ect. Since this system is a spray nozzle that creates a puddle of developer on the substrate the spray is on for 10s. to cover any type of substrates, however this procedure starts the actual development, and the "idle" time is hence shortened accordingly. The system is setup so that 10s. in the Developer E-beam correlates to 10s. in a beaker, however all designs are different and larger or smaller structures may need different development times.

Cold development

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We do have the possibility of making cold development, to get more vertical and smoother sidewalls. We have a coolplate that can go down to -2°C, with a ramp of app. 3 °C/min.

Is it recommended to make a dose test, if one is to transfer from ordinary development to cold.

Procedure

1. Pour developer suited for your resist into a small blue cap bottle, and label it, remember to mark it with lot number, date and your name.
2. Leave this small bottle of developer in the fridge in Cx1 at least overnight to acclimatize.
3. Take the coolplate located in D3 (see picture) and connect it in Fumehood 10 (E-beam) place it on the sink-lid to keep a good airflow.
4. Hold left button on the front panel of the cool plate and set temperature with up/down arrows.
5. The cool plate can go down to -2°C, and the fridge is +5°C hence use a beaker and pour cold developer into it and place on the coolplate, leave it to acclimatize for the desired temperature.

Development time in cold development, should be subject to testing, depending on structure size and density, but is comparable with "normal" development times.

When developing at low temperatures, condensation can occur

Remember to clean up after you are done

Proximity Error Correction

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Even though the electron beam diameter is below 5 nm, the feature and pitch resolution in resist is limited by the forward and backward scattering of the electrons. The forward scattering depends on the electron acceleration voltage, the resist material and thickness. The backward scattering depends on the electron acceleration voltage and the substrate material [2], [3].

As the travel distance of backscattered electrons is fairly large, e-beam patterned structures will be influenced by adjacent e-beam patterned structures, i.e. a proximity effect. These proximity effects can be avoided either by simulating a proximity error correction (PEC) in BEAMER or by using the right stack of e-beam resist.

Proximity Error Correction (PEC) in BEAMER

BEAMER is endowed with a software that corrects for proximity errors in the e-beam exposure. You can read more about this function in the BEAMER manual here and in the BEAMER presentation here BEAMERPresentation.pdf‎.

The proximity error correction require a forward and a backward range parameter, alfa and beta, and a ratio of backscattered energy to the forward scattered energy, eta. As alfa depends on the electron acceleration voltage, which is constant at 100kV, alfa is in BEAMER fixed to 0.007. Help to find beta and eta can be found here.

Alternatively, a point-spread function can be used in BEAMER to calculate the optimised dose-variation.

Trilayer resist stack

As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [4]. This reists stack has not yet been tested at DTU Nanolab. A process flow for this procedure can be found here Process_Flow_Trilayer_Ebeam_Resist.docx‎, but please contact Lithography before use.

Charging of non-conductive substrates

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All substrates are grounded to the cassette when properly loaded. In a non-conducting substrate, the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist.

If you wish to investigate the charge dissipation using other methods than below, please contact Lithography.

ESPACER

Espacer is a chemical that works as a discharging layer; it is spun onto the wafer on top of the resist and easily rinsed off the wafer after e-beam exposure. Visit this page for more information: Espacer

Aluminum coating

At DTU Nanolab, we recommend to use a thin (20 nm) layer of thermally evaporated aluminum on top of the e-beam resist. Preferably, the thickness of Al and the e-beam dose should be optimised to the features you wish to e-beam pattern [5]. A good starting point is 20 nm Al; from here dose and development can be optimised to reach the resolution and feature size required.

The process flow for a standard e-beam exposure on CSAR with Al on top can be found here Process Flow CSAR with Al.

Literature on E-beam Lithography

• Handbook of Microlithography, Micromachining, and Microfabrication, Volume 1: Microlithography, P. Rai-Choudhury (Editor), chapter 2 (p 139 – 250). Link to book can be found here: http://www.cnf.cornell.edu/cnf_spietoc.html
• Lithography, Wiley, 2011: Chapter 3, Electron Beam Lithography by Stefan Landis: http://onlinelibrary.wiley.com/doi/10.1002/9781118557662.ch3/summary