Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using ASE

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The ASE is now the "dirty" plasma etcher at Nanolab meaning small amount of metals are allowed to be exposed by the plasma. That calls for recipes etching Silicon oxide and silicon nitride as well as silicon in this machine.

CF4/H2 chemistry - SiO2 etch

*Unless otherwise stated, all content in this section was done by Maria Farinha@DTU Nanolab, April 2023

Due to the instability of older SiO2 etch recipes, 1SIOICP1 and TSIO2_02, new recipes are being developed, with a CF4/H2 chemistry. Two new recipes were created, to replace the older ones, CF4ICP and CF4lowCP. The first one aims for thicker etches, with higher ER, while the other is a slower etch, dedicated to thinner layers.

Parameter Recipe name: CF4ICP Recipe name: CF4lowCP
Coil Power [W]
800
150
Platen Power [W]
15
25
Platen temperature [oC]
20
20
CF4 flow [sccm]
22.5
22.5
H2 flow [sccm]
22.5
22.5
Pressure [mTorr]
2.5
2.5
  • CF4 and H2 flow values were changed in order to find the best recipe regarding selectivity between SiO2 and the resist and also the uniformity.


Results of these recipes:

CF4ICP SiO2 ER (nm/min) Selectivity (SiO2:resist) Si3N4 ER (nm/min) SixN ER (nm/min)
22.5 CF4 + 22.5 H2
68
1.13

The uniformity considers a 100mm wafer, calculated with 5 points.

CF4lowCP SiO2 ER (nm/min) Uniformity (SiO2 etch) Selectivity (SiO2:resist) Si3N4 ER (nm/min) SixN ER (nm/min)
22.5 CF4 + 22.5 H2



CHF3/H2 chemistry - SiO2/SiN etch

*Unless otherwise stated, all content in this section was done by Maria Farinha@DTU Nanolab, April 2023

Due to the instability of older SiO2 etch recipes, 1SIOICP1 and TSIO2_02, new recipes are being developed, with a CHF3/H2 chemistry. Two new recipes were created are CHF3_t1 and CHF3_t2. The first one aims for thicker etches, with higher ER, while the other is a slower etch, dedicated to thinner layers.

Parameter Recipe name: CHF3_t1 Recipe name: CHF3_t2
Coil Power [W]
800
150
Platen Power [W]
15
25
Platen temperature [oC]
20
20
CHF3 flow [sccm]
22.5
22.5
H2 flow [sccm]
22.5
22.5
Pressure [mTorr]
2.5
2.5

CHF3 and H2 flow values were changed in order to find the best recipe regarding selectivity SiO2/resist and also the uniformity.


CHF3_t1 SiO2 ER (nm/min) Uniformity (SiO2 etch) Selectivity (SiO2:resist) Si3N4 ER (nm/min) SixN ER (nm/min)
22.5 CHF3 + 22.5 H2
47.3
12%
1.8
-
-

The uniformity considers a 100mm wafer, calculated with 5 points.

CHF3_t2 SiO2 ER (nm/min) Uniformity (SiO2 etch) Selectivity (SiO2:resist) Si3N4 ER (nm/min) SixN ER (nm/min)
22.5 CHF3 + 22.5 H2
27
-
2^
-
-

^This recipe etches resist at high rates depending on the size of the structures. For example, if the structures are smaller, the resist will be eroded away quicker. It's advised to have at least 1:1 ratio of resist to the SiO2 to be etched.


C4F8/H2 chemistry - SiO2 etch

Unless otherwise stated, all content in this section was done by Maria Farinha@DTU Nanolab, May 2023

This recipe was taken from the ICP Metal etch, with a slight difference in the platen temperature. This recipe wasn't yet tested for very deep etches. Be aware of that when processing for more than 10min. You should not process it for more than 20min in a single run, if needed do more runs, you should wait a bit in between processes.

Parameter Recipe name: SiO2_ICP
Coil Power [W] 1000
Platen Power [W] 200
Platen temperature [oC] 20
C4F8 flow [sccm] 10
H2 flow [sccm] 28
Pressure [mTorr] 2.5

Results with a non-patterned wafer

Recipe Recipe: SIO2_ICP SIO2_ICP on stoic Nit (Si3N4) SIO2_ICP on low-stress Nit (SixN)
Etch rate 121 nm/min

(18.07.2023 mfarin @ DTU nanolab)

194 nm/min

(24.05.2023 mfarin @ DTU nanolab)

Results with a patterned wafer

Material to be etched Recipe: SIO2_ICP SIO2_ICP on stoic Nit SIO2_ICP on low-stress Nit SIO2_ICP on Si
Etch rate in SiO2 155 nm/min in the center, 125nm/min in the edges

(03052023 mfarin @ DTU nanolab)

Etch rate in resist (AZ 5214E) 108 nm/min in the center, 98nm/min in the edges

(03052023 mfarin @ DTU nanolab)

Selectivity (SiO2:resist) 1.45
Etch rate in silicon
Profile Images

  • More tests will be done regarding silicon and silicon nitride, since this recipe can be used for overetch.


Tests with sample on carrier

By Berit Herstrøm @nanolab, January-Marts 2018

SiO2 etch with resist mask, sample on carrier (Si carrier)

Our old RIE systems have to the end of their lives been used a lot for etching samples that could not be clamped/cooled in the ICP systems. The higher plasma density in the ICP's make their processes more tough on resist masks, probably because of too much heating. Therefor the ICP's are using cooled bottom electrodes with He back side cooling to keep the temperature low for the resist mask to survive. When decommissioning the RIE's (RIE1 and RIE2) a need came for developing recipes on the ICP's that could etch Si, SiO2 and SiN without clamping/cooling the substrates. This part considers etching in SiO2. First an attempt to run the ASE in RIE mode using only the platen generator was made. This resulted in not so nice sidewalls due to redeposition and slow etches, see below. After that the development focused on running with both low coil power and low platen power.

SiO2 etch with resist mask, sample on carrier (Si carrier) in the RIE mode using CF4/CHF3/H2 chemistry

By Berit Herstrøm @nanolab, January-Marts 2018

In this study a design of experiments (DOE) were done in RIE mode, meaning using only the platen power and avoiding the coil power. This was to keep the temperature of the substrate low without helium backside cooling the sample.

Results for the DOE

Conclusion

The conclusion of this work was that using that platen power alone was giving too much re-deposition on the sidewalls leading to very rough sidewalls. To reduce/avoid it the platen power had to be lowered so much that the etch rate got unacceptably low. There for next study included the coil power.

SiO2 etch with resist mask, sample on carrier (Si and Al carrier) in the ICP mode using C4F8/H2/He chemistry

By Berit Herstrøm @danchip, January-Marts 2018

The challenge was to develop a SiO2 etching recipe that can be used for samples on a carrier. Samples that cannot be clamped and cooled. The goal was to keep a good selectivity to the resist mask and get a vertical sidewall, without getting a lot of redeposition on the sidewalls. The testing regime was using both the coil power and the platen power with C4F8/H2 chemistry. Please be aware that some of these recipes are no longer allowed to be run due to too high power without cooling may damage the electrode!

Take a look at development flow and the results here: Media:ASE SiO2 etch on carrier ICP C4F8 H2 no He rev02.pdf . Zoom in to read and see the images: (Ctrl + "+")

Effect chart made from the observations in this study

Effect chart of increasing input factors Etch rate Selectivity to resist Sidewall Other Observations
Coil power ↑ ↑ ↓ At high coil powers the sample surface gets so hot that it affects the resists too much. The resist changes form at the high powers and the plasma/ions breaks through the resist at different rates, leaving the SiO2 surface very rough. 150W seems to be good for etching about 1 µm of SiO2. Remember this is for samples that are NOT clamped and cooled.
Platen power ↑ ↑ ↓ High Platen power also makes the sample surface too hot so it affects the resist in a bad way. Keeping it very low when the coil power is also kept low gives a very low etch rate. At least up to 25 W seems OK, with coil power 150W
Total flow rate ↑ ↓ ↑ We are here in the pumping rate limited regime where the etch rate goes down with the flow rate. But at the same time the selectivity goes up because the residence times gets shorter. This probably leads to CF2/F increasing and should improve the selectivity.
H2/C4F8 ↑ ↓ ↑ H/F increasing also increases the selectivity. H reacts with F to form HF and this makes the F/C decrease giving higher selectivity. Too must H2 gives too much polymer formation and this will stop the etch completely, so it is a matter of finding a balance. Even before the polymer deposition get so high that it stops the etch it still produces so much deposition on the sidewalls that it affects the etch profile, take a look at number 15, 18 and 25 in the development flow:Media:ASE SiO2 etch on carrier ICP C4F8 H2 no He rev02.pdf. The critical dimension changes (line width increases), the sidewalls get rounded but it can prevent trenching.



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