Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch): Difference between revisions
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====Transparent wafers==== | ====Transparent wafers==== | ||
Transparent wafers are a | Transparent wafers are a challenge for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test successfully. | ||
# The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer | # The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer | ||
#The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before | #The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transferring it into chamber or deposit a more conducting/semiconducting layer on the backside of the wafer (could be silicon, maybe Chromium, please ask). 1-2µm P-Si may be enough, maybe even less. | ||
==An overview of the performance of AOE and some process related parameters== | ==An overview of the performance of AOE and some process related parameters== | ||