Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-3: Difference between revisions

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=== Other etch processes ===
=== Other etch processes ===


*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch|Continuous nanostructure etches including nano1.42]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/DUVetch|Etch processes with DUV masks]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Barc|BARC etches]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Isotropic|Isotropic etches]]


More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.
More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.

Revision as of 12:45, 2 December 2021

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Pegasus 3 - 150mm silicon etching

THIS PAGE IS UNDER CONSTRUCTION

The tool is ready for user training.

The Pegasus 3 cassette station (left), operator station (center) and support computer with Picoscope process monitoring.


The user manual(s) is available, technical information and contact information can be found in LabManager:

Equipment info in LabManager

Process information

Standard recipes


Hardware changes

Compared to a standard SPTS DRIE Pegasus chamber, the Pegasus 3 has had the same modifications as the Pegasus 1 with the exception of the Claritas EPD system. The changes are listed below.

The original (fast switching and with a maximum flow of 1200 sccm) SF6 MFC was causing problems for a long a time so it was replaced by two new MFC's:

  • SF6-1: Fast switching MFC for Bosch processes with a maximum flow rate of 600 sccm. It sits in the position of the old 1200 sccm MFC on top of the plasma source.
  • SF6-2: Normal MFC for continuous processes with a maximum flow rate of 100 sccm. It is installed in the gas cabinet next to the Ar MFC.


Other etch processes

More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.



Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click here.

Internal Nanolab Process log for Pegasus 3

Process log at Nanolab [1]