Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4: Difference between revisions
No edit summary |
|||
Line 11: | Line 11: | ||
[[Image:Twinx.jpg |frame|left|x300px|The twin Pegasi (3 and 4) have just been rolled into the lab on July 3rd 2018. ]] | [[Image:Twinx.jpg |frame|left|x300px|The twin Pegasi (3 and 4) have just been rolled into the lab on July 3rd 2018. ]] | ||
'''Feedback to this page: | |||
[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus click here]''' | |||
[[Category: Equipment |Etch DRIE]] | |||
[[Category: Etch (Dry) Equipment|DRIE]] | |||
= DRIE-Pegasus 1= | |||
[[Image:DRIE-Pegasus.jpg |frame|left|x300px|The DRIE-Pegasus 1 load lock and cassette loader in the Nanolab cleanroom A-1]] | |||
'''The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:''' | |||
Equipment info in [http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=265| LabManager] | |||
== Process information == | |||
'''[[Specific Process Knowledge/Etch/DRIE-Pegasus/StandardRecipes|Standard recipes]]''' | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/processA|Process A (Large trench): 80 µm wide trench etched down to a depth of 150 µm]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/processB|Process B (Via etch): 30 µm diameter via etched down to a depth of 100 µm]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/processC|Process C (Nano etch): 50-300 nm posts]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/processD|Process D (Micro stamp) ''Please note that this process has changed'' ]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/SOIetch|SOI etch]] | |||
'''Hardware changes''' | |||
A few hardware modifications have been made on the Pegasus since it was installed in 2010. The changes are listed below. | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/showerheadchange|Change of showerhead in December 2014]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/picoscope|Addition of Picoscope oscilloscope system for process monitoring in February 2017]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Claritas|Addition of a Claritas optical endpoint system in June 2018]] | |||
=== Other etch processes === | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch|Continuous nanostructure etches including nano1.42]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/DUVetch|Etch processes with DUV masks]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Barc|BARC etches]] | |||
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Isotropic|Isotropic etches]] | |||
More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information. | |||
<!-- *[[Specific Process Knowledge/Etch/DRIE-Pegasus/slopedsidewalls|Etches that produce positively sloped sidewalls for imprinting purposes]] --> | |||
<!-- *[[Specific Process Knowledge/Etch/DRIE-Pegasus/Waferthinning| Maskless reduction of wafer thicknesses]] --> | |||
<!-- *[[Specific Process Knowledge/Etch/DRIE-Pegasus/VeeryDeeep| Very deep etching]] --> | |||
=== Advanced Processing - Henri Jansen style === | |||
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch silicon nanostructures|Etch silicon nanostructures ]] | |||
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch high aspect ratio silicon microstructures|Etch high aspect ratio silicon microstructures ]] | |||
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch 3 dimensional silicon microstructures|Etch 3 dimensional silicon microstructures]] | |||
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch black silicon|Etch black silicon]] | |||
* [[Specific Process Knowledge/Etch/DRIE-Pegasus/Using OES to monitor etch process|Using OES to monitor etch process]] | |||
=== Wafer bonding === | |||
To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]]. | |||
=== Acceptance test === | |||
The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found [[Media:Pegasus_AcceptanceTest.pdf|here]]. | |||
'''Characterisation of etched trenches''' | |||
Comparing differences in etched trenches requires a set of common parameters for each trench. Click [[Specific Process Knowledge/Etch/DRIE-Pegasus/TrenchCharacterisation|'''HERE''']] to find more information about the parameters used on the DRIE-Pegasus process development. | |||
'''Internal Nanolab Process log for Pegasus 1''' | |||
Process log at Nanolab [http://labintra.nanolab.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus] |
Revision as of 14:23, 25 March 2020
Feedback to this page: click here
Pegasus 4 - 150mm silicon oxide and silicon nitride etching
The tool is currently being installed - we hope that it will be available in the second half of 2019. Some gasses needed for silicon oxide etching has not been installed yet
Feedback to this page: click here
DRIE-Pegasus 1
The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:
Equipment info in LabManager
Process information
Hardware changes
A few hardware modifications have been made on the Pegasus since it was installed in 2010. The changes are listed below.
Other etch processes
More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.
Advanced Processing - Henri Jansen style
- Etch silicon nanostructures
- Etch high aspect ratio silicon microstructures
- Etch 3 dimensional silicon microstructures
- Etch black silicon
- Using OES to monitor etch process
Wafer bonding
To find information on how to bond wafers or chips to a carrier wafer, click here.
Acceptance test
The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found here.
Characterisation of etched trenches
Comparing differences in etched trenches requires a set of common parameters for each trench. Click HERE to find more information about the parameters used on the DRIE-Pegasus process development.
Internal Nanolab Process log for Pegasus 1
Process log at Nanolab [1]