Specific Process Knowledge/Etch/KOH Etch

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Si etch - Anisotropic silicon etch

KOH belongs to the family of anisotropic Si-etchants based on aqueous alkaline solutions. The anisotropy stems from the different etch rates in different crystal directions. The {111}-planes are almost inert whereas the etch rates of e.g. {100}- and {110}-planes are several orders of magnitude faster.

KOH-etching is a highly versatile and cheap way to realize micro mechanical structures if you can live with the necessary Si₃N₄- or SiO₂-masking materials and the potassium contamination of the surface. The latter necessitates in most cases a wet post-clean ('7-up' or RCA-clean) if the wafer is to be processed further.

At Danchip we use as a standard a 28 wt% KOH. The etch rate - and the selectivity towards a SiO₂-mask - is depending on the temperature. We normally use T=80 ^oC but may choose to reduce this to e.g. 60 ^oC or 70 ^oC in case of a high-precision timed etch (e.g. defining a thin membrane). In some cases we recommend to saturate the standard 28 wt% KOH with IPA with an etch temperature at T=70 ^oC (reduce evaporation of IPA). One example is for boron etch-stop, where the selectivity towards the boron-doped silicon is improved compared to the standard etch. Etching with IPA added to the KOH solution can be done in KOH fumehood.

• Different places to do anisotropic wet silicon etch
• 
  Wetbench 01: Si etch, for Si etch of 4" and 6" wafers using KOH. Positioned in cleanroom D-3.
• 
  Fume hood 06: Si etch, for Si etch of 4" and 6" wafers using KOH. Positioned in cleanroom D-3. This is used for wafers that are considered dirty.

The user manuals, quality control procedures and results, user APVs, technical information and contact information can be found in LabManager:

Si Etch 1: KOH info page in LabManager,

Si Etch 2: KOH info page in LabManager,

Si Etch 3: KOH info page in LabManager

Process Information

• QC info for standard KOH baths
• How to mix KOH
• Crystal orientation dependency

KOH etching baths

Key facts for the different etch baths available at Danchip are resumed in the table:

Equipment		Si Etch 01: KOH	Si Etch 02: KOH	Si Etch 03: KOH
Purpose	Etch of Silicon in 28 wt% KOH	Etch of Silicon in 28 wt% KOH	Etch of Silicon in 28 wt% KOH	Etch of Silicon in 28 wt% KOH The bath is dedicated wafer with electroplated Nickel or otherwise dirty wafers
	Link to safety APV and KBA	see APV here see KBA here	see APV here see KBA here	see APV here see KBA here
Performance	Etch rates in crystalline silicon (100)	0.4 µm/min (60 °C) 0.7 µm/min (70 °C) 1.3 µm/min (80 °C)	0.4 µm/min (60 °C) 0.7 µm/min (70 °C) 1.3 µm/min (80 °C)	0.4 µm/min (60 °C) 0.7 µm/min (70 °C) 1.3 µm/min (80 °C)
	Etch rates in crystalline silicon (110)	2.5 µm/min (80 °C)	2.5 µm/min (80 °C)	2.5 µm/min (80 °C)
	Etch rates in Thermal SiO2	Theoretical values: 1.2 nm/min (60 °C) 6 nm/min (80 °C)	Theoretical values: 1.2 nm/min (60 °C) 6 nm/min (80 °C)	Theoretical values: 1.2 nm/min (60 °C) 6 nm/min (80 °C)
	Etch rates in other oxides	.	yannickseis@nbi.ku nov. 2017 @80 °C: BPSG from PECVD4: 311nm in about 3 min Waveguide oxide from PECVD4: 320nm etched in 26 min TEOS oxide from furnace: 300nm etched in 11 min	.
	Etch rates in SiN
	Roughness	Typical: 100-600 Å	Typical: 100-600 Å	May be high due to contamination and poor controlled concentration of the KOH solution
	Anisotropy	The etch rate is very dependent on the crystal orientation of the silicon.	The etch rate is very dependent on the crystal orientation of the silicon.	The etch rate is very dependent on the crystal orientation of the silicon.
Process parameter range	Chemical solution	Mixing ratios giving 28 wt% KOH solutions KOH:H2O - 500 g : 1000 ml, when using pills KOH:H2O - 1000 ml: 1200 ml, when using premixed 50% KOH solution	Mixing ratios giving 28 wt% KOH solutions KOH:H2O - 500 g : 1000 ml, when using pills KOH:H2O - 1000 ml: 1200 ml, when using premixed 50% KOH solution	Custom made
	Temperature	Max 80 °C (standard etch)	Max 80 °C	Max 80 °C
Substrates	Batch size	1-25 wafers at a time	1-25 wafers at a time	1-7 wafers at a time
	Size of substrate	4”-6" wafers	4”-6" wafers	2” wafers 4” wafers 6” wafers Small pieces
	Allowed materials	Silicon Silicon oxide Silicon (oxy)nitride	Silicon Silicon oxide Silicon (oxy)nitride	All except for Polymers
	Masking material	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2

¹ Measured by Eric Jensen from DTU-Nanotech, October 2013.