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LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions

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DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers
4,346 edits
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|-
|-
!1.1
!1.1
|Plasma surface treatment
|RCA clean
|To ensure clean surface, the 100 mm Si wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|Before Si deposition in LPCVD furnace, the quartz (fused silica) wafers need to be cleaned
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]]
|[[image:00_zero (1)_nanogratings.JPG|250x350px|center|]]
|[[image:Zero1.jpg|250x350px|center|]]
|-
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|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.2
!1.2
|DUV Resist patterning
|LPCVD of Si
|DUV
|LPCVD deposition of 300 nm amorphous Si
|[[Specific_Process_Knowledge/Lithography/DUVStepperLithography|DUV Stepper Lithography]].  
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]].  
|[[image:00_zero (2)_nanogratings.JPG|250x350px|center|]]
|[[image:Zero2.jpg|250x350px|center|]]
|-
|-


|-
|-
!1.3
!1.3
|Deep reactive ion etching (DRIE)
|Si anisotropic wet etch
|DRIE; [[Specific_Process_Knowledge/Etch/DRIE-Pegasus/DUVetch|Recipe: PolySOI10]]
|Removal of the Si from the back side of the wafer.
| [[Specific_Process_Knowledge/Etch/DRIE-Pegasus|DRIE Pegasus]].
| [[Specific_Process_Knowledge/Etch/KOH_Etch|KOH]].
|[[image:00_zero (3)_nanogratings.JPG|250x350px|center|]]
|[[image:Image1_Si_on_SiO2.jpg|250x350px|center|]]
|-
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!1.4
!1.4
|Plasma surface treatment
|Plasma surface treatment
|To ensure that remainings of DUV resist are gone, samples are treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|To ensure that all organic remainings are gone, wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]].
|
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]]
<br clear="all" />
|
|
|-
|-
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|-
|-
!1.5
!1.5
|Scanning Electron Microscopy inspection
|E-beam lithography (EBL)
|By cleaving the sample it is possible to inspect DRIE etched Si trenches in cross-sectional mode
|Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure.
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
[[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOL_JBX-9500FSZ|JEOL JBX-9500 Electron-beam]]  
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]  
<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:Image2_ebeam_on_Si.jpg|250x350px|center]]
|[[image:Si_trenches_nanogratings.jpg|250x350px|center]]
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.6
!1.6
|Atomic Layer Deposition of either Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub>
|Advanced Silicon Etching
|Deposition carried at 150C.Thickness is 90 nm.
|Creating sacrificial silicon template.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipes used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/Al2O3_deposition_using_ALD#Al2O3_recipe_for_deposition_on_high_aspect_ratio_structures| Al2O3T]] and [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] .
|
|[[image:00_zero (4)_nanogratings.JPG|250x350px|center]]
[[Specific_Process_Knowledge/Etch/ASE_(Advanced_Silicon_Etch)|ASE]]  
<br clear="all" />
|[[image:Image3_ASE_of_SI.jpg|250x350px|center]]
|-
|-


|-
|-
!1.7
!1.7
|Scanning Electron Microscopy inspection
|Scanning Electron Microscopy inspection
|By cleaving the sample it is possible to inspect ALD coatings deposited on Si trenches in cross-sectional mode
|The fabricated template inspects by SEM
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
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<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_coating_nanogratings.jpg|250x350px|center]]  
|[[image:Si_template_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.8
!1.8
|Opening of deposited Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> top layers.
|Plasma surface treatment
|Etching happens using ICP Metal etcher with Cl<sub>2</sub>/BCl<sub>3</sub> process gasses.
|To ensure that all organic remainings are gone, template is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].
|
|[[image:00_zero (6)_nanogratings.JPG|250x350px|center]]
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]]
<br clear="all" />
|
|-
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|-
|-
!1.9
!1.9
|Atomic Layer Deposition of TiO<sub>2</sub>
|Deposition carried at 150C.Thickness is approx. 90 nm.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] .
|[[image:Image4_ALD_of_SI_template.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.10
|Ion beam etching (IBE).
|Opening of deposited TiO<sub>2</sub> top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching.
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:Image5_ALD_Ar_sputtering.jpg|250x350px|center]]
|-
|-
!1.11
|Scanning Electron Microscopy inspection
|Scanning Electron Microscopy inspection
|By cleaving the sample it is possible to inspect ICP etcher results Si trenches in cross-sectional mode
|SEM inspection of ALD deposition and IBE etching.
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
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<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_top_removal_nanogratings.jpg|250x350px|center]]  
|[[image:top_removal_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.10
!1.12
|Selective etch of Si between ALD Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> coatings.
|Selective etch of Si between ALD TiO<sub>2</sub> coatings.
|Si etching proceeds using ICP Metal etcher with isotropic process based on SF<sub>f</sub> process gas.
|Si etching proceeds using Reactive Ion Etching (RIE) with isotropic process based on SF<sub>f</sub> process gas.
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].  
||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]].  
|[[image:00_zero (7)_nanogratings.JPG|250x350px|center]]
|[[image:Image6_ALD_Final_structure.jpg|250x350px|center]]
|-
|-




|-
|-
!1.11
!1.13
|Scanning Electron Microscopy inspection of fabricated structure.
|Scanning Electron Microscopy inspection of fabricated structure.
|Proof of final result.
|Proof of final result.
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<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_grating_nanogratings.jpg|250x350px|center]]  
|[[image:Si_removal_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|- style="background:#BCD4E6; color:black"
!1.12
|Ion beam etching. (Optional)
|Additional shape of the top part. 20 mijn etch using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage shoud be placed to 0<sup>o</sup> degree. SEM cross section is used for inspection
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:image1004_nanogratings.jpg|250x350px|center]]
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|-
|}
|}
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