Specific Process Knowledge/Etch/DRIE-Pegasus

The SPTS Pegasus in the Danchip cleanroom

Important: New rules (as of August 2011) for using the Pegasus

Until August 2011 processing at the Pegasus was complicated by frequent losses of wafers during transfer operations. It is evident that the instrument is much more susceptible to misalignments of the carousel than expected. A service engineer from SPTS has made a thorough realigning of the instrument that we hope will last a long time. We have therefore introduced a new set of rules that all users should be taught during a new training session mandatory for all users regardless of prior experience. The rules are:

1. All wafers must be processed using the MACS cassette loader. The only exceptions are bonded wafers and 150 mm wafers - see point 3. Batch recipes must be prepaired - even for single wafer trial runs.
2. The backsides of the wafers must be absolutely clean: Wipe with IPA or blow dry the backside of every wafer.
3. Loading bonded wafers (only bonded wafers and 6" wafers) using the load lock must be done with utmost care avoiding to change the position of the carousel.
4. Processing using the MACS may be done either manually or automatically.

Please contact Roy, Peter or Jonas to make a training session.

The DRIE Pegasus at Danchip

The DRIE Pegasus is a state-of-art silicon dry etcher. It offers outstanding performance in terms of etch rate, uniformity etc. This page will provide some clues.

The Bosch process in the DRIE-Pegasus

The DRIE-Pegasus takes the well established Bosch process known from the ASE a significant step further. In the ASE the Bosch process has two cycles, etch and passivation. During each cycle the process parameters are kept constant (This is, at least, that is the intention - the reality is that the ideal square function is rarely achieved during process parameter changes).

• In the passivation cycle, a C₄F₈ plasma is formed using the RF coil power only and a teflon-like coating is created on all surfaces thus protecting the sidewalls in the subsequent etch cycle.
• In the etch cycle
  • the ion bombardment driven by the platen power first removes the passivation layer on the surfaces directly exposed to the ions (i.e. horizontal surfaces)
  • then as the bottom of the structures are opened the etch of silicon itself starts.

The etch cycle may be split into three parts, Boost, Delay and Main, where process parameters such as pressure, gas flows or RF powers have different values.

Here, it is clear that one can distinguish two phases of the etch cycle; one where the ion bombardment removes the polymer and one where the actual etching of silicon takes place. Considering what process conditions are favorable we realize that

1. the ion bombardment requires a low pressure in order for the ions to have a long mean free path and hence good directionality. Also, a high platen power is required to drive the ion bombardment.
2. a higher pressure during the etch increases the density of reactive species and hence the etch rate. Since a high platen power is no longer necessary to drive the ion bombardement, lowering it will reduce the impact on the masking material thus improving the selectivity.

These conflicting demands are the same on the ASE. However, with hardware improvements on the DRIE-Pegasus such as

• fast response digtal MFC's mounted on top of the process chamber itself to shorten the gas line
• fast APC valve
• fast RF power supply

the etch and deposition cycles may be split into three separate phases, called Delay, Boost and Main. Following the arguments from above, the third phase (Delay) may be thought of as a short delay that ensures a very low pressure (and thus extremely good ion directionality) before the ion bombardment. The standard etches on the Pegasus only make use of up to two phases.

Processing options on the Pegasus

The Pegasus has a lot of advanced processing options.

1. Multiplexing: As described above, the multiplexed Bosch process may have the etch or passivation cycle each split into three separate phases: Delay, Boost and Main.
2. Ramping:Using the ramp option one can change process parameters linearly over the course of each processing step.
3. Process steps: Stich any number of processing steps with different parameters to make one continuous process.
4. Hardware: The Pegasus has several hardware settings:
   1. Spacers : The distance to the plasma source may be changed by using different spacers.
   2. Baffle and funnel: The funnel inside the chamber helps to focus the plasma/ions towards the electrode. They may be taken out but don't expect this option to be part of the parameters that you can change in your experiments.

This gives an infinite process parameter space....

The standard processes: Processes A, B, C, D and SOI

The instrument was accepted on the basis of the performance of 5 processes. These standard processes are described below.

Most commonly used processes on DRIE-Pegasus

Process name	Type	Purpose	Conditions during original runs				Best usage
			Feature	Mask material	Etch load	Comments
Process A	Bosch	Fast etch	80 µm trench	Photo resist	12-13 % on 6" wafer
Process B	Bosch	Fast etch	30 µm diameter via	Photo resist	12-13 % on 6" wafer

How to read the SPTS notation on process recipes

To understand the SPTS short hand notation on process recipes look at two examples from the etch cycle of step1 of the Process A described below:

1. The Platen power has the setting 120 >> 140 (1.5s) 45 - it is to be interpreted as:
   1. In the first 1.5 seconds of the every cycle the platen power has a value that is ramped (indicated by >>) from 120 W initially to 150 W in the end
   2. During the remainder of the cycle the platen power is kept constant at 45 W.
2. The Pressure has the setting 25 (1.5 s) 90 >> 150 - it is to be interpreted as:
   1. In the first 1.5 seconds the pressure is constant at 25 mtorr.
   2. During the remainder of the cycle the pressure has i higher value that is ramped from 90 initially to 150 mtorr in the last etch cycle.

Process A

Process A is labelled Large trench (80μm wide) 150μm depth. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.

Process A: Recipe, specifications and results

Process B

Process A is labelled Via (30μm diameter) 100μm depth. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.

Process B: Recipe, specifications and results

Process C

Process A is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.

Process C: Recipe, specifications and results

Process D

Process D is labelled Micro stamp etch.

In the acceptance test the process was run on a 100 mm wafer with 50 % etch load.

Process D: Recipe, specifications and results

SOI etch

The SOI etch uses the Low frequency (LF) platen generator to minimize the notching at buried stop layers such as the BOX layer in a SOI wafer.

SOI etch: Recipe, specifications and results

Other processes

Nanoetching

Nanoetch

Sloped sidewalls

For injection molding purposes

User manuals

• The Danchip user manual from LabManager is found >Here<.
• The user manual provided by SPTS can be found here >HERE<

Hardware information

Hardware Information - Overview.

Hardware Information - Detailed.

The Advantages the Pegasus has over existing Si etchers.

Robot Handling System Information .

Process applications

The acceptance test for the DRIE-Pegasus system, April 2010.

MEMS in Aerospace.

Bio Medical.

MEMS in Energy.

Nanotechnology.

Packaging Applications.

General Applications.

Further info:

FAQ (Under construction)