Specific Process Knowledge/Lithography/Aligners/Aligner: Maskless 01 processing: Difference between revisions
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<br>The alignment test with 4 alignment marks mimics the shift from the field alignment test, but the deviation on the Y-axis is very large, probably due to the surprising -40ppm scaling measured by the alignment routine. Keep in mind that the wafer has not been unloaded between the two exposures. Something is going on with the Y-axis. | <br>The alignment test with 4 alignment marks mimics the shift from the field alignment test, but the deviation on the Y-axis is very large, probably due to the surprising -40ppm scaling measured by the alignment routine. Keep in mind that the wafer has not been unloaded between the two exposures. Something is going on with the Y-axis. | ||
<br>Aligning with 2 marks on the X-axis seems to fix this problem, and shows an average error similar to the camera offset, with a tight distribution across the wafer. However, aligning using 2 marks on the Y-axis introduces a large shift in Y. This shift is repeated if 2 alignment marks along the X-axis on the top half of the wafer is used, but it is fixed if 2 marks along the X-axis on the bottom half are used, or if 2 marks on the Y-axis is used with the first mark on the bottom half of the wafer. Again, there seems to be something strange going on with the Y-axis. | <br>Aligning with 2 marks on the X-axis seems to fix this problem, and shows an average error similar to the camera offset, with a tight distribution across the wafer. However, aligning using 2 marks on the Y-axis introduces a large shift in Y. This shift is repeated if 2 alignment marks along the X-axis on the top half of the wafer is used, but it is fixed if 2 marks along the X-axis on the bottom half are used, or if 2 marks on the Y-axis is used with the first mark on the bottom half of the wafer. Again, there seems to be something strange going on with the Y-axis. | ||
<br>In an attempt to fix the large deviation on the Y-axis when using 4 alignment marks, a test was made adding an alignment mark in 0;0 as the first mark during alignment. This did not have any beneficial effect, as the deviation on the Y-axis values is similar to the deviation from the 4 mark test. | |||
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The alignment test with 4 alignment marks shows a +40ppm scaling on the X-axis, as well as a 0.1mRad shearing of the axes. The result is a decent alignment in X, but a shift in Y as well as a relatively large deviation. The raw data shows the deviation in Y is due to a -40ppm scaling along the Y-axis, as seen in the MLA1-MLA1 test with 4 marks, suggesting that the scaling in Y is consistently overestimated. | The alignment test with 4 alignment marks shows a +40ppm scaling on the X-axis, as well as a 0.1mRad shearing of the axes. The result is a decent alignment in X, but a shift in Y as well as a relatively large deviation. The raw data shows the deviation in Y is due to a -40ppm scaling along the Y-axis, as seen in the MLA1-MLA1 test with 4 marks, suggesting that the scaling in Y is consistently overestimated. | ||
<br>Aligning using only 2 marks yields acceptable shifts in the center of the wafer, but very large shifts in X towards the edges, as evidenced by the 7.4µm deviation in X. The raw data suggests that this deviation is mainly due to a 0.2mRad tilt in the Y-axis, which corresponds well with the 0.1mRad shearing measured using 4 marks. There is also a (-)40ppm scaling along the X-axis, again similar to what was measured during 4 mark alignment. Even a 5mm chip would be affected by the 0.2mRad tilt, so clearly 4 mark alignment is needed when aligning to a pattern that was not exposed using MLA1. | <br>Aligning using only 2 marks yields acceptable shifts in the center of the wafer, but very large shifts in X towards the edges, as evidenced by the 7.4µm deviation in X. The raw data suggests that this deviation is mainly due to a 0.2mRad tilt in the Y-axis, which corresponds well with the 0.1mRad shearing measured using 4 marks. There is also a (-)40ppm scaling along the X-axis, again similar to what was measured during 4 mark alignment. Even a 5mm chip would be affected by the 0.2mRad tilt, so clearly 4 mark alignment is needed when aligning to a pattern that was not exposed using MLA1. | ||
<br>Attempting to fix the shift in Y when using 4 alignment marks by adding 0;0 as the first mark unfortunately makes no difference. However, when MLA3 is used to align to a pattern printed using MLA1, the resulting spread of alignment errors is quite small, suggesting that MAL3 is somehow better at compensating for the differences between the two machines than MLA1. | |||
=Optimal use of the maskless aligner= | =Optimal use of the maskless aligner= | ||