Specific Process Knowledge/Lithography/nLOF: Difference between revisions
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==PEB baking time investigation== | |||
While 60 s @ 110°C is adequate for Si substrates, less thermally conductive substrates (glass, III-V materials, chips bonded to carrier), have shown problems using the standard PEB recipe.<br> | While 60 s @ 110°C is adequate for Si substrates, less thermally conductive substrates (glass, III-V materials, chips bonded to carrier), have shown problems using the standard PEB recipe.<br> | ||
These problems were largely solved by increasing the PEB time to 120 s. Tests (on Aligner: Maskless 02) have shown that the lithographic performance of nLOF on Si is improved when using 120 s @ 110°C PEB (less stitching, less bias, more negative profile). A small report on the tests can be found [[media:nLOF_PEBtime_2019.pdf|'''here''']]. | These problems were largely solved by increasing the PEB time to 120 s. Tests (on Aligner: Maskless 02) have shown that the lithographic performance of nLOF on Si is improved when using 120 s @ 110°C PEB (less stitching, less bias, more negative profile). | ||
A small report on the tests can be found [[media:nLOF_PEBtime_2019.pdf|'''here''']]. | |||
==Development== | ==Development== | ||