Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-1: Difference between revisions
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To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]]. | To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]]. | ||
'''Characterisation of etched trenches''' | '''Characterisation of etched trenches''' |
Revision as of 14:08, 2 May 2023
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Unless otherwise stated, all content on this page was created by Jonas Michael-Lindhard, DTU Nanolab
DRIE-Pegasus 1
The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:
Equipment info in LabManager
Process information
Hardware changes
A few hardware modifications have been made on the Pegasus since it was installed in 2010. The changes are listed below.
Other etch processes
More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.
Advanced Processing - Henri Jansen style
- Etch silicon nanostructures
- Etch high aspect ratio silicon microstructures
- Etch 3 dimensional silicon microstructures
- Etch black silicon
- Using OES to monitor etch process
Wafer bonding
To find information on how to bond wafers or chips to a carrier wafer, click here.
Characterisation of etched trenches
Comparing differences in etched trenches requires a set of common parameters for each trench. Click HERE to find more information about the parameters used on the DRIE-Pegasus process development.
Internal Nanolab Process log for Pegasus 1
Process log at Nanolab [1]