Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
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Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines. | Image:S0_oxide_05.jpg|Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines. | ||
Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part. <br> Etch time 15 min | Image:S4_06.jpg|Sample S4: Profile view. The recipe InP etch has been used. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample. <br> The sidewall profile is quit vertical in the lower part. <br> Etch time 15 min | ||
Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N"=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> | Image:S5_05.jpg|Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N"=30 sccm Cl2=30 sccm. <br> The sample has been run on a SiO2 carrier wafer. <br> There is not much CD change compared to the oxide mask before the etch. <br> It seems like the SiO2 mask is gone. <br> The sidewall profile is overcutting probably due to too little passivation. <br> Etch time 10 min | ||
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Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quit high | Image:S4_30dg_2_05.jpg|Sample S4: The sidewall roughness on the sample S4 is quit high | ||