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| *[[Specific Process Knowledge/Etch/DRIE-Pegasus/FAQ|Miscellaneous information]] | | *[[Specific Process Knowledge/Etch/DRIE-Pegasus/FAQ|Miscellaneous information]] |
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| ==Equipment performance and process related parameters==
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| {| border="2" cellspacing="0" cellpadding="2"
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|
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| !colspan="2" border="none" style="background:silver; color:black;" align="center"|Equipment
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| |style="background:WhiteSmoke; color:black"|<b>DRIE-Pegasus</b>
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| |-
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| !style="background:silver; color:black;" align="center" width="80"|Purpose
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| |style="background:LightGrey; color:black"| Dry etch of
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| |style="background:WhiteSmoke; color:black"|
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| * Silicon
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| * Barc
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| |-
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| !style="background:silver; color:black" align="center" valign="center" rowspan="2"|Performance
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| |style="background:LightGrey; color:black"|Etch rates
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| |style="background:WhiteSmoke; color:black"|
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| * Standard processes A and B up to 15 µm/min depending on etch load and feature size
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| * Other processes: Any number from 200 nm/min to 10 µm/min
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| |-
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| |style="background:LightGrey; color:black"|Uniformity
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| |style="background:WhiteSmoke; color:black"|
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| * For standard processes better than 3 % across a 150 mm wafer.
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| |-
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| !style="background:silver; color:black" align="center" valign="center" rowspan="4"|Process parameter range
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| |style="background:LightGrey; color:black"|RF powers
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| |style="background:WhiteSmoke; color:black"|
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| * Coil Power 5 kW
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| * Platen power 300/500 W (HF/LF)
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| |-
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| |style="background:LightGrey; color:black"|Gas flows
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| |style="background:WhiteSmoke; color:black"|
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| * SF<sub>6</sub>: 0 to 1200 sccm
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| * O<sub>2</sub>: 0 to 200 sccm
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| * C<sub>4</sub>F<sub>8</sub>: 0 to 400 sccm
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| * Ar: 0 to 283 sccm
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| |-
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| |style="background:LightGrey; color:black"|Pressure and temperature
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| |style="background:WhiteSmoke; color:black"|
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| * Pressure range 4 to 250 mTorr
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| * Temperature range -20 to 30 degrees C
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| |-
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| |style="background:LightGrey; color:black"|Process options
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| |style="background:WhiteSmoke; color:black"|
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| * Bosch processes with etch and dep cycles possibly split into three individually controllable parts
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| * Parameter ramping during process steps
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| * SOI option to reduce notching at buried
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| |-
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|
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| !style="background:silver; color:black" align="center" valign="center" rowspan="3"|Substrates
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| |style="background:LightGrey; color:black"|Batch size
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| |style="background:WhiteSmoke; color:black"|
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| *<nowiki>#</nowiki> small samples on carriers
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| *<nowiki>#</nowiki> 50 mm wafers: Bonded to carriers
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| *<nowiki>#</nowiki> 100 mm wafers: Up to 18 wafers in a batch process
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| *<nowiki>#</nowiki> 150 mm wafers: 1 wafer
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| |-
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| | style="background:LightGrey; color:black"|Allowed materials
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| |style="background:WhiteSmoke; color:black"|
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| * Silicon wafers
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| * Quartz wafers need a (semi)conducting layer for clamping
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| |-
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| | style="background:LightGrey; color:black"|Possible masking materials
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| |style="background:WhiteSmoke; color:black"|
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| * AZ photoresist
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| * zep resist
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| * DUV stepper resist (barc + krf)
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| * Oxides and nitrides
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| * Aluminium (only very mild processes such as process C and nanoetches)
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| |}
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