LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions
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|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.2 | !1.2 | ||
|LPCVD of Si | |Low-Pressure Chemical Vapour Deposition (LPCVD) of Si | ||
|LPCVD deposition of 300 nm amorphous Si | |LPCVD deposition of 300 nm amorphous Si | ||
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]]. | |[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]]. | ||
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|- | |- | ||
!1.5 | !1.5 | ||
|E- | |E-Beam Lithography (EBL) | ||
|Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure. | |Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure. | ||
| | | | ||
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|- | |- | ||
!1.9 | !1.9 | ||
|Atomic Layer Deposition of TiO<sub>2</sub> | |Atomic Layer Deposition (ALD) of TiO<sub>2</sub> | ||
|Deposition carried at 150C.Thickness is approx. 90 nm. | |Deposition carried at 150C.Thickness is approx. 90 nm. | ||
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] . | ||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] . | ||
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|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.10 | !1.10 | ||
|Ion | |Ion Beam Etching (IBE). | ||
|Opening of deposited TiO<sub>2</sub> top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching. | |Opening of deposited TiO<sub>2</sub> top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching. | ||
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]] | |[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]] | ||
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|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.12 | !1.12 | ||
|Selective etch of Si between ALD TiO<sub>2</sub> coatings. | |Selective etch of Si between ALD TiO<sub>2</sub> coatings. (Reactive Ion Etching) | ||
|Si etching proceeds using Reactive Ion Etching (RIE) with isotropic process based on SF<sub>6</sub> process gas. | |Si etching proceeds using Reactive Ion Etching (RIE) with isotropic process based on SF<sub>6</sub> process gas. | ||
||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]]. | ||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]]. | ||