Specific Process Knowledge/Thin film deposition/Furnace LPCVD TEOS: Difference between revisions
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[[Category: Equipment|Thin film LPCVD TEOS]] | [[Category: Equipment|Thin film LPCVD TEOS]] | ||
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[[Category: Furnaces|LPCVD TEOS]] | [[Category: Furnaces|LPCVD TEOS]] | ||
==LPCVD TEOS | ==B3 LPCVD TEOS furnace== | ||
[[Image:160904_danchip_4538.jpg|300x300px|thumb|B3 | [[Image:160904_danchip_4538.jpg|300x300px|thumb|B3 LPCVD TEOS furnace. Positioned in cleanroom B-1]] | ||
DTU Nanolab has one LPCVD (Low Pressure Chemical Vapor Deposition) TEOS furnace, in LabManager "Furnace: LPCVD TEOS (B3)". The furnace is a Tempress horizontal furnace (installed in 1995). The process is a batch process, where TEOS oxide can be deposited on up to 15 4" wafers at a time. | DTU Nanolab has one LPCVD (Low Pressure Chemical Vapor Deposition) TEOS furnace, in LabManager "Furnace: LPCVD TEOS (B3)". | ||
The furnace is a Tempress horizontal furnace (installed in 1995). The process is a batch process, where TEOS oxide can be deposited on up to 15 4" wafers at a time. | |||
TEOS is tetraethoxysilane, and TEOS oxide is a silicon dioxide based on this reactive chemical that during deposition condenses on the sample surface. The deposition takes place at a temperature of 712-720 <sup>o</sup>C (there is a small temperature gradient over the furnace tube). | TEOS is tetraethoxysilane, and TEOS oxide is a silicon dioxide based on this reactive chemical that during deposition condenses on the sample surface. The deposition takes place at a temperature of 712-720 <sup>o</sup>C (there is a small temperature gradient over the furnace tube). | ||
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It is possible to anneal TEOS oxide layers to increase the density and thus improve the electrical properties as well as the chemical resistance. The electrical characteristics may also be improved by the addition of O<sub>2</sub> during the deposition process. | It is possible to anneal TEOS oxide layers to increase the density and thus improve the electrical properties as well as the chemical resistance. The electrical characteristics may also be improved by the addition of O<sub>2</sub> during the deposition process. | ||
LPCVD TEOS oxide has an excellent step coverage and is very good for trench filling, however very small nanometer trenched and/or very deep trenches will be challenging to fill. The film thickness is very uniform | LPCVD TEOS oxide has an excellent step coverage and is very good for trench filling, however very small nanometer trenched and/or very deep trenches will be challenging to fill. The film thickness over the wafers is very uniform. | ||
More information about the TEOS oxide deposition process can be found here: | More information about the TEOS oxide deposition process can be found here: | ||
[[Specific Process Knowledge/Thin film deposition/ | [[Specific Process Knowledge/Thin film deposition/Furnace LPCVD TEOS|Deposition of TEOS oxide using LPCVD]] | ||
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*[https://labmanager.dtu.dk/view_binary.php?class=MiscDocument&id=19&name=Furnace+computer+manual+April+2024.pdf See LabManager (requires a login)] | *[https://labmanager.dtu.dk/view_binary.php?class=MiscDocument&id=19&name=Furnace+computer+manual+April+2024.pdf See LabManager (requires a login)] | ||
==Process | ==Process knowledge== | ||
Please take a look at the process side for deposition of TEOS oxide: | Please take a look at the process side for deposition of TEOS oxide: | ||
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==Overview of the performance of the LPCVD TEOS furnace and some process related parameters== | ==Overview of the performance of the LPCVD TEOS furnace and some process related parameters== | ||
{| border="2" cellspacing="0" cellpadding=" | {| border="2" cellspacing="0" cellpadding="10" | ||
|- | |- | ||
!style="background:silver; color:black | !colspan="2" border="none" style="background:silver; color:black" align="center"|Purpose | ||
|style="background:LightGrey; color:black"| | |style="background:LightGrey; color:black"|'''Deposition of TEOS oxide''' | ||
Deposition of TEOS oxide | |||
|- | |- | ||
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Performance | !style="background:silver; color:black" align="center" valign="center" rowspan="3"|Performance | ||
|style="background:LightGrey; color:black"|Film thickness | |style="background:LightGrey; color:black"|Film thickness | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"| | ||
* | *Up to 3000 nm | ||
|- | |- | ||
|style="background:LightGrey; color:black"|Step coverage | |style="background:LightGrey; color:black"|Step coverage | ||
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|style="background:LightGrey; color:black"|Gas flows | |style="background:LightGrey; color:black"|Gas flows | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"| | ||
*TEOS: ~50 sccm. <i>The exact flow is not know - the setpoint is much lower than 50 sccm, | *TEOS (tetraethoxysilane): ~50 sccm. <i>The exact flow is not know - the setpoint is much lower than 50 sccm, because the MFC is not calibrated for TEOS</i> | ||
*O<sub>2</sub>: 0 sccm | *O<sub>2</sub>: 0 sccm | ||
|- | |- | ||
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| style="background:LightGrey; color:black"|Substrate materials allowed | | style="background:LightGrey; color:black"|Substrate materials allowed | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"| | ||
*Silicon and fused silica/quartz wafers. <i>New wafers supplied by Nanolab | *Silicon and fused silica/quartz wafers. <i>New wafers supplied by Nanolab can to go directly into the furnace</i> | ||
*Wafers from the A stack, B stack and E stack furnaces. <i> The wafers have to go directly into the furnace </i> | *Wafers from the A stack, B stack and E stack furnaces. <i> The wafers have to go directly into the furnace </i> | ||
*Processed wafers (only allowed materials - see the cross contamination information in LabManager). <i> The wafers have to be RCA cleaned </i> | *Processed wafers (only allowed materials - see the cross contamination information in LabManager). <i> The wafers have to be RCA cleaned </i> | ||