Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4: Difference between revisions

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==Pegasus 4 - 150mm silicon oxide and silicon nitride etching==
==Pegasus 4 - 150mm silicon oxide and silicon nitride etching==
[[Image:Peg3and4 front 2.JPG |frame|right|x250px|The DRIE-Pegasus3 and DRIE-Pegasus4 operator station and cassette loading stations, {{photo1}}]]


 
DRIE-Pegasus 4 is dedicated Silicon oxide and Silicon nitride etching. It is originally designed for silicon etching but gas mass flow controllers has been changed to optimize silicon oxide and silicon nitride etching. The system is setup for 6" wafers. Sampler samples has to be bonded to a 6" carrier to be etched in the system. 
[[Image:Peg3and4 front 2.JPG |frame|left|x300px|The DRIE-Pegasus3 and DRIE-Pegasus4 operator station and cassette loading stations, {{photo1}}]]


'''The user manual and contact information can be found in LabManager:'''  
'''The user manual and contact information can be found in LabManager:'''  
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*[[/Barc Etch|Barc Etch]]
*[[/Barc Etch|Barc Etch]]
*[[/SiO2 Etch|SiO2 Etch]]
*[[/SiO2 Etch|SiO2 Etch]]
*[[/Nitride Etch|Nitride etch with SiO2 etch recipes]]
*[[/Slow etch|Slow etch of silicon nitride and silicon oxide]]
*[[/Slow etch|Slow etch of silicon nitride and silicon oxide]]



Latest revision as of 10:38, 22 August 2023

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Pegasus 4 - 150mm silicon oxide and silicon nitride etching

The DRIE-Pegasus3 and DRIE-Pegasus4 operator station and cassette loading stations, Photo: DTU Nanolab internal

DRIE-Pegasus 4 is dedicated Silicon oxide and Silicon nitride etching. It is originally designed for silicon etching but gas mass flow controllers has been changed to optimize silicon oxide and silicon nitride etching. The system is setup for 6" wafers. Sampler samples has to be bonded to a 6" carrier to be etched in the system.

The user manual and contact information can be found in LabManager:

DRIE Pegasus 4 in LabManager - requires login

Process information

Standard recipes



Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click here.