Latest revision as of 12:00, 28 June 2023

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Unless otherwise stated, the content of this page was created by the dry etch group at DTU Nanolab

DRIE-Pegasus 1

The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:

Equipment info in LabManager

Process information

Standard recipes

Process A (Large trench): 80 µm wide trench etched down to a depth of 150 µm

Process B (Via etch): 30 µm diameter via etched down to a depth of 100 µm

Process C (Nano etch): 50-300 nm posts

Process D (Micro stamp) Please note that this process has changed

SOI etch

Hardware changes

A few hardware modifications have been made on the Pegasus since it was installed in 2010. The changes are listed below.

Change of showerhead in December 2014

Addition of Picoscope oscilloscope system for process monitoring in February 2017

Addition of a Claritas optical endpoint system in June 2018

Other etch processes

DREM processes

Continuous nanostructure etches including nano1.42

Etch processes with DUV masks

Isotropic etches

More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jmli@dtu.dk) for more information.

Advanced Processing - Henri Jansen style

Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click here.

Characterisation of etched trenches

Comparing differences in etched trenches requires a set of common parameters for each trench. Click HERE to find more information about the parameters used on the DRIE-Pegasus process development.

Internal Nanolab Process log for Pegasus 1

Process log at Nanolab [1]

Template:Global:Infobox Software/MediaWiki

@@ Line 3: / Line 3: @@
 [[Category: Equipment |Etch DRIE]]
 [[Category: Etch (Dry) Equipment|DRIE]]
+{{contentbydryetch}}
+<!--Checked for updates on 28/6-2023 - ok/jmli -->
 = DRIE-Pegasus 1=
-[[Image:DRIE-Pegasus.jpg |frame|left|x300px|The DRIE-Pegasus 1 load lock and cassette loader in the Nanolab cleanroom A-1]]
+[[Image:DRIE-Pegasus.jpg |frame|left|x300px|The DRIE-Pegasus 1 load lock and cassette loader in the Nanolab cleanroom A-1. {{photo1}} ]]
 '''The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:'''
@@ Line 57: / Line 61: @@
 === Advanced Processing - Henri Jansen style ===
 * [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch silicon nanostructures|Etch silicon nanostructures ]]
 * [[Specific Process Knowledge/Etch/DRIE-Pegasus/Etch high aspect ratio silicon microstructures|Etch high aspect ratio silicon microstructures ]]
@@ Line 67: / Line 72: @@
 To find information on how to bond wafers or chips to a carrier wafer, click [[Specific Process Knowledge/Etch/DryEtchProcessing/Bonding| here]].
-=== Acceptance test ===
-The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found [[Media:Pegasus_AcceptanceTest.pdf|here]].
 '''Characterisation of etched trenches'''
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 Process log at Nanolab [http://labintra.nanolab.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus]
-{{URL}}
+{{global:Infobox Software/MediaWiki}}
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