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LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/AZO pillars: Difference between revisions

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<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br>
<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br>
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br>
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br></i>
The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br></i>


====Procces flow description====
=Fabrication of Hyperbolic Metamaterials by ALD: AZO Pillars=


The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br>
== Procces flow description ==
Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O<sub>2</sub> at 1100 °C, resulting in a 200 nm SiO<sub>2</sub> layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO<sub>2</sub> surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from
Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O<sub>2</sub> at 1100 °C, resulting in a 200 nm SiO<sub>2</sub> layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO<sub>2</sub> surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from
Tempress) based on SiH<sub>4</sub> at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates.
Tempress) based on SiH<sub>4</sub> at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates.
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!1.3
!1.3
|LPCVD deposition of Si. (Optional step. Needs only if SOI substrates requires)
|LPCVD deposition of Si. (Optional step. Needs only if SOI substrates requires)
|LPCVD of amorphous silicon using [[Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_polysilicon/Deposition_of_polysilicon_using_LPCVD/Standard_recipes,_QC_limits_and_results_for_the_6"_polysilicon_furnace|AMORPOLY]] recipe in 6" Furnace LPCVD PolySilicon.
|LPCVD of amorphous silicon using [[Specific Process Knowledge/Thin film deposition/Furnace LPCVD PolySilicon/Standard recipes, QC limits and results for the 6" polysilicon furnace|AMORPOLY]] recipe in 6" Furnace LPCVD PolySilicon.
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" Furnace LPCVD PolySilicon]].
|[[Specific Process Knowledge/Thin film deposition/Furnace LPCVD PolySilicon| 6" Furnace LPCVD PolySilicon]].
|[[image:3_1_SOI.jpg|250x350px|center|]]
|[[image:3_1_SOI.jpg|250x350px|center|]]
|-
|-
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