Specific Process Knowledge/Etch/Etching of Silicon Oxide: Difference between revisions

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== Comparing silicon oxide etch methods at Danchip ==
== Comparing silicon oxide etch methods at DTU Nanolab ==
There are a broad varity of silicon oxide etch methods at Danchip. The methodes are compared here to make it easier for you to compare and choose the one that suits your needs.  
There are a broad varity of silicon oxide etch methods at DTU Nanolab. The methodes are compared here to make it easier for you to compare and choose the one that suits your needs.  


*[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]]
*[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]]
*[[/SiO2 etch using RIE1 or RIE2|SiO2 etch using RIE2]]
 
*[[/SiO2 etch using ASE|SiO2 etch using ASE]]
*[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]]
*[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]]
*[[/SiO2 etch using AOE|SiO2 etch using AOE]]
*[[/SiO2 etch using AOE|SiO2 etch using AOE]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4|SiO2 etch with DRIE Pegasus 4]]
*[[/SiO2 etch using ASE|SiO2 etch using ASE]]
*[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]]
*[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]]
*[[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
*[[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
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!
!
![[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide etch (BHF/HF)]]
![[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide etch (BHF/HF)]]
![[Specific Process Knowledge/Etch/RIE (Reactive Ion Etch)|RIE2 (Reactive Ion Etch)]]
![[Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch)|ASE]]
![[Specific Process Knowledge/Etch/III-V RIE |III-V RIE]]
![[Specific Process Knowledge/Etch/III-V RIE |III-V RIE]]
![[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)|AOE (Advanced Oxide Etch)]]
![[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)|AOE (Advanced Oxide Etch)]]
![[Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4|DRIE Pegasus 4]]
![[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP metal]]
![[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP metal]]
![[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
![[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
![[Specific Process Knowledge/Etch/HF Vapour Phase Etch|HF Vapour Phase Etch]]


|-
|-
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|
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*Anisotropic etch: almost vertical sidewalls
*Anisotropic etch: almost vertical sidewalls
*We prefer that SiO2 etch takes place in the AOE, since it is a very polymeric process an the ICP is not heating as much as the AOE.
|
*Anisotropic etch: almost vertical sidewalls
*We prefer that SiO2 etch takes place in the AOE or Pegasus 4.
|
|
*Primarily for pure physical etch by sputtering with Ar-ions
*Primarily for pure physical etch by sputtering with Ar-ions
|
*Gas phase HF etching with ethanol as carrier
|-
|-


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*Aluminium
*Aluminium
*Chromium (Please try to avoid this)
*Chromium (Please try to avoid this)
|
*Photoresist
*DUV resist
*E-beam resist
*Si
*Silicon Nitride
*Chromium (ask for permission)
|
|
*Photoresist
*Photoresist
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*Aluminium
*Aluminium
*Chromium
*Chromium
*Ti
|
|
*Any material that is accepted in the machine
*Any material that is accepted in the machine
|
*Aluminium
*Aluminium oxide
*Polysilicon
|-
|-


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*~75 nm/min (Thermal oxide) in BHF
*~75 nm/min (Thermal oxide) in BHF
*~90 nm/min (Thermal oxide) in SIO Etch
*~80 nm/min (Thermal oxide) in BOE 7:1 Etchant VLSI with Surfactant
*~25 nm/min (Thermal oxide) in 5%HF
*~25 nm/min (Thermal oxide) in 5%HF
*~6 nm/min (Thermal oxide) in 1%HF
*~3-4µm/min in 40%HF
*~3-4µm/min in 40%HF
|
|
*Process dependent
*Process dependent
*Tested range: ~20nm/min - ~120nm/min  
*Tested range: ~20nm/min - ~250nm/min  
|
|
*Process dependent
*Process dependent
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*Process dependent
*Process dependent
*Tested range: ~60nm/min - ~550nm/min
*Tested range: ~60nm/min - ~550nm/min
|
*Process dependent
<500nm/min
|
|
*Process dependent
*Process dependent
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*Process dependent
*Process dependent
*Tested once ~22nm/min
*Tested once ~22nm/min
|-
|
 
*Sample and load dependent
*Expected range: 12 - 175 nm/min
|-
|-
|-style="background:LightGrey; color:black"
|-style="background:LightGrey; color:black"
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*What can be fitted in a plastic beaker
*What can be fitted in a plastic beaker
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*As many small samples as can be fitted on the 100mm carrier.
*As many small samples as can be fitted on the 100mm carrier (bad/no cooling!).
*<nowiki>#</nowiki>1 100mm wafer (or smaller with carrier)
*<nowiki>#</nowiki>1 100mm wafer (or smaller with carrier)
*<nowiki>#</nowiki>1 150mm wafer (only when set up for 150mm)  
*<nowiki>#</nowiki>1 150mm wafer (only when set up for 150mm)  
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*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)
|
*As many small samples as can be bonded on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer bonded on a 150mm wafer
*<nowiki>#</nowiki>1 100 mm wafer bonded on a 150nm wafer
*<nowiki>#</nowiki>1 150 mm wafers
|
|
*As many small samples as can be fitted on a 150mm wafer
*As many small samples as can be fitted on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer fitted on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer fittesd on a 150mm wafer
*<nowiki>#</nowiki>1 100 mm wafer fitted on a 150nm wafer
*<nowiki>#</nowiki>1 100 mm wafer fitted on a 150nm wafer
*<nowiki>#</nowiki>1 150 mm wafers
*<nowiki>#</nowiki>1 150 mm wafers
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*<nowiki>#</nowiki>1 150 mm wafers with special carrier
*<nowiki>#</nowiki>1 150 mm wafers with special carrier
*<nowiki>#</nowiki>1 200 mm wafer
*<nowiki>#</nowiki>1 200 mm wafer
|
*Pieces
*<nowiki>#</nowiki>1 50 mm wafer
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 150 mm wafer
|-
|-
|-style="background:WhiteSmoke; color:black"
|-style="background:WhiteSmoke; color:black"
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*No limits cross contamination wise
*No limits cross contamination wise
|
|
*[http://labmanager.dtu.dk/function.php?module=XcMachineaction&view=edit&MachID=19 Please take a look in the cross contamination sheet in LabManager for details]
*[http://labmanager.dtu.dk/function.php?module=XcMachineaction&view=edit&MachID=105 Please take a look in the cross contamination sheet in LabManager for details]
*Silicon
*Silicon
*Silicon Oxide
*Silicon Oxide
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*DUV resist
*DUV resist
*E-beam resist
*E-beam resist
*Other metals if they cover less than 5% of the wafer area (ONLY RIE2!)
*Other metals if they cover less than 5% of the wafer area
*Quartz/fused silica
*Quartz/fused silica
|
|
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*Aluminium
*Aluminium
*Chromium (try to avoid it)
*Chromium (try to avoid it)
*Quartz/fused silica
|
*[http://labmanager.dtu.dk/function.php?module=XcMachineaction&view=edit&MachID=456 Please take a look in the cross contamination sheet in LabManager for details]
*Silicon
*Silicon Oxide
*Silicon Nitride
*Silicon Oxynitride
*Photoresist
*DUV resist
*E-beam resist
*Chromium
*Quartz/fused silica
*Quartz/fused silica
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*Polymers
*Polymers
*Capton tape
*Capton tape
|
*[http://labmanager.dtu.dk/function.php?module=XcMachineaction&view=edit&MachID=458 Please take a look in the cross contamination sheet in LabManager for details]
*Silicon
*Silicon oxides
*Aluminium
|-
|-
|}
|}


<br clear="all" />
<br clear="all" />
==Dry etch with Hard mask==
''By Martin Lind Ommen - ''fall 2016'' '' <br>
Testing selectivities for SiO<sub>2</sub> etching with hard masks on AOE and ICP metal with different recipes.All tests are done with 100% etching load<br>
[[File:Dry etching by Martin Lind Ommen Fall 2016.png|600px]]<br>
MLO_psi is the version of SiO2_psi on labadviser that is shown under low line with reduction.<br>
The recipe ICP is on ICP metal call: A SiO2 etch with C4F8 with resist mask<br>
I had problems with this recipe - it gave polymer on the surface, therefor I do not have more info on that.<br>

Latest revision as of 08:27, 22 August 2023

Unless anything else is stated, everything on this page, text and pictures are made by DTU Nanolab.

All links to Kemibrug (SDS) and Labmanager Including APV and QC requires login.

Feedback to this page: click here

Comparing silicon oxide etch methods at DTU Nanolab

There are a broad varity of silicon oxide etch methods at DTU Nanolab. The methodes are compared here to make it easier for you to compare and choose the one that suits your needs.

Compare the methods for Silicon Oxide etching

Wet Silicon Oxide etch (BHF/HF) ASE III-V RIE AOE (Advanced Oxide Etch) DRIE Pegasus 4 ICP metal IBE/IBSD Ionfab 300 HF Vapour Phase Etch
Generel description
  • Isotropic etch
  • Anisotropic etch: vertical sidewalls
  • Anisotropic etch: vertical sidewalls
  • Premarily for III-V samples
  • Anisotropic etch: vertical sidewalls
  • Anisotropic etch: almost vertical sidewalls
  • Anisotropic etch: almost vertical sidewalls
  • We prefer that SiO2 etch takes place in the AOE or Pegasus 4.
  • Primarily for pure physical etch by sputtering with Ar-ions
  • Gas phase HF etching with ethanol as carrier
Possible masking materials
  • Photoresist
  • PolySilicon
  • Silicon nitride (LPCVD)
  • Blue film
  • Cr/Au for deeper etches (plastic beaker)
  • Photoresist
  • DUV resist
  • E-beam resist
  • Silicon
  • Silicon Nitride
  • Metals if they cover less than 5% of the wafer area
  • Photoresist
  • DUV resist
  • E-beam resist
  • Aluminum
  • Silicon
  • Silicon Nitride
  • Photoresist
  • DUV resist
  • E-beam resist
  • Silicon
  • Silicon Nitride
  • Aluminium
  • Chromium (Please try to avoid this)
  • Photoresist
  • DUV resist
  • E-beam resist
  • Si
  • Silicon Nitride
  • Chromium (ask for permission)
  • Photoresist
  • DUV resist
  • E-beam resist
  • Si
  • Silicon Nitride
  • Aluminium
  • Chromium
  • Any material that is accepted in the machine
  • Aluminium
  • Aluminium oxide
  • Polysilicon
Etch rate range
  • ~75 nm/min (Thermal oxide) in BHF
  • ~80 nm/min (Thermal oxide) in BOE 7:1 Etchant VLSI with Surfactant
  • ~25 nm/min (Thermal oxide) in 5%HF
  • ~6 nm/min (Thermal oxide) in 1%HF
  • ~3-4µm/min in 40%HF
  • Process dependent
  • Tested range: ~20nm/min - ~250nm/min
  • Process dependent
  • Tested range: ~1nm/min - ~30nm/min
  • Process dependent
  • Tested range: ~60nm/min - ~550nm/min
  • Process dependent

<500nm/min

  • Process dependent
  • Tested range: ~40nm/min - ~200nm/min
  • Process dependent
  • Tested once ~22nm/min
  • Sample and load dependent
  • Expected range: 12 - 175 nm/min
Substrate size
  • #1-25 100mm wafers in our 100mm bath
  • What can be fitted in a plastic beaker
  • As many small samples as can be fitted on the 100mm carrier (bad/no cooling!).
  • #1 100mm wafer (or smaller with carrier)
  • #1 150mm wafer (only when set up for 150mm)
  • Up to 20cm in diameter
  • As many small samples as can be fitted on a 100mm wafer
  • #1 50 mm wafer fitted on a 100mm wafer
  • #1 100 mm wafer
  • #1 150 mm wafers (only when the system is set up to 150mm)
  • As many small samples as can be bonded on a 150mm wafer
  • #1 50 mm wafer bonded on a 150mm wafer
  • #1 100 mm wafer bonded on a 150nm wafer
  • #1 150 mm wafers
  • As many small samples as can be fitted on a 150mm wafer
  • #1 50 mm wafer fittesd on a 150mm wafer
  • #1 100 mm wafer fitted on a 150nm wafer
  • #1 150 mm wafers
  • As many samples as can be securely fitted on a up to 200mm wafer
  • #1 50 mm wafer with special carrier
  • #1 100 mm wafer with special carrier
  • #1 150 mm wafers with special carrier
  • #1 200 mm wafer
  • Pieces
  • #1 50 mm wafer
  • #1 100 mm wafer
  • #1 150 mm wafer
Allowed materials

In the dedicated bath:

  • Silicon
  • Silicon Oxide
  • Silicon Nitride
  • Silicon Oxynitride
  • Photoresist
  • Blue film

In a plastic beaker:

  • No limits cross contamination wise


Dry etch with Hard mask

By Martin Lind Ommen - fall 2016
Testing selectivities for SiO2 etching with hard masks on AOE and ICP metal with different recipes.All tests are done with 100% etching load

MLO_psi is the version of SiO2_psi on labadviser that is shown under low line with reduction.
The recipe ICP is on ICP metal call: A SiO2 etch with C4F8 with resist mask
I had problems with this recipe - it gave polymer on the surface, therefor I do not have more info on that.