LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/AZO pillars: Difference between revisions
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= | '''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/LabAdviser/Technology_Research/Fabrication_of_Hyperbolic_Metamaterials_using_Atomic_Layer_Deposition/AZO_pillars click here]''' | ||
<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br> | |||
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br></i> | |||
=Fabrication of Hyperbolic Metamaterials by ALD: AZO Pillars= | |||
The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br> | |||
== Procces flow description == | |||
Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O<sub>2</sub> at 1100 °C, resulting in a 200 nm SiO<sub>2</sub> layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO<sub>2</sub> surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from | Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O<sub>2</sub> at 1100 °C, resulting in a 200 nm SiO<sub>2</sub> layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO<sub>2</sub> surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from | ||
Tempress) based on SiH<sub>4</sub> at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates. | Tempress) based on SiH<sub>4</sub> at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates. | ||
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<gallery caption="" widths="500px" heights="600px" perrow="2"> | <gallery caption="" widths="500px" heights="600px" perrow="2"> | ||
image:Fabrication_shematic_AZO_pillars_eves2.jpg|Figure 1. Schematics of the fabrication flow. a) Home-made SOI substrates. b) Deep-UV lithography. Resist spin coating, baking, exposure and developing. c) DRIE etching, fabrication of initial Si template. d) ALD deposition of D25 AZO at 250 °C. Partial deposition will lead to fabrication of tubes, while complete filling will create full pillars. e) Removal of the top AZO layer by Ar+ sputtering. f) Silicon host removal using conventional RIE process. | image:Fabrication_shematic_AZO_pillars_eves2.jpg|Figure 1. Schematics of the fabrication flow. a) Home-made SOI substrates. b) Deep-UV lithography. Resist spin coating, baking, exposure and developing. c) DRIE etching, fabrication of initial Si template. d) ALD deposition of D25 AZO at 250 °C. Partial deposition will lead to fabrication of tubes, while complete filling will create full pillars. e) Removal of the top AZO layer by Ar+ sputtering. f) Silicon host removal using conventional RIE process. | ||
image:AZO_structures_fab_supplementary_eves.jpg|Figure 2. SEM images, bird-eye-view. a) AZO pillars and b) AZO tubes. | image:AZO_structures_fab_supplementary_eves.jpg|Figure 2. SEM images, bird-eye-view. a) AZO pillars, and b) AZO tubes. | ||
</gallery> | </gallery> | ||
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|LPCVD deposition of Si. (Optional step. Needs only if SOI substrates requires) | |LPCVD deposition of Si. (Optional step. Needs only if SOI substrates requires) | ||
|LPCVD of amorphous silicon using [[ | |LPCVD of amorphous silicon using [[Specific Process Knowledge/Thin film deposition/Furnace LPCVD PolySilicon/Standard recipes, QC limits and results for the 6" polysilicon furnace|AMORPOLY]] recipe in 6" Furnace LPCVD PolySilicon. | ||
|[[ | |[[Specific Process Knowledge/Thin film deposition/Furnace LPCVD PolySilicon| 6" Furnace LPCVD PolySilicon]]. | ||
|[[image:3_1_SOI.jpg|250x350px|center|]] | |[[image:3_1_SOI.jpg|250x350px|center|]] | ||
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|Scanning Electron Microscopy inspection. | |Scanning Electron Microscopy inspection. | ||
|By cleaving the sample it is possible to inspect ALD coatings deposited | |By cleaving the sample it is possible to inspect ALD coatings deposited in Si holes in cross-sectional mode. | ||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]] | [[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]] | ||