LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions
Appearance
| (5 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/LabAdviser/Technology_Research/Fabrication_of_Hyperbolic_Metamaterials_using_Atomic_Layer_Deposition/TiO2_Q_plates click here]''' | |||
<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br> | |||
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br> | |||
The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br></i> | |||
====Procces flow description==== | ====Procces flow description==== | ||
A 500 μm | A 500 μm thick wafer of silica (SiO<sub>2</sub>) goes through RCA clean and low-pressure chemical vapor deposition (LPCVD) (furnace from Tempress) based on SiH<sub>4</sub> (silane) at 560<sup>◦</sup>C to form a layer of 300 nm of amorphous silicon (Si) [Fig. 1]. The back side of deposited Si was etched using KOH wet etch. In order to remove residues from the etching process, it was performed oxygen plasma cleaning. A CSAR resist was spin-coated to the thickness of 150 nm, followed by exposure of Electron Beam Lithography (EBL) (JEOL JBX-9500 Electron-beam) generating a mask with concentric ring patterns. After development, the wafer was submitted to advanced silicon etch (ASE). To form the trenches of the TiO<sub>2</sub> structures, a thin film of TiO<sub>2</sub> was deposited using the ALD technique in a hot-wall system (Picosun R200), working with 2000 cycles at 150<sup>◦</sup>C [Fig.1]. The precursors used were titanium tetrachloride (TiCl<sub>4</sub>) and H<sub>2</sub>O (supplied by Strem Chemicals Equipment). The process was followed by Ar<sup>+</sup> ion beam etching (IBE) on both sides of the wafer to remove excess of ALD deposited material. At the top most TiO<sub>2</sub> layer the physical sputtering of the sample using Ar<sup>+</sup> ions was performed in order to get access to Si core. On the backside, the Ar<sup>+</sup> ions were used to remove the deposited TiO<sub>2</sub>. Finally, we performed a reactive ion etch on silicon, leaving only the TiO<sub>2</sub> structures. The final system comprehends a base of SiO<sub>2</sub> with nano-structures of TiO<sub>2</sub> on it. Figure 2 shows the image of the system taken using scanning electron microscope (SEM) and conventional optical microscope. Figure 3 illustrates SEM cross-sectional image of the prepared Q-plate . | ||
| Line 29: | Line 36: | ||
|- | |- | ||
!1.1 | !1.1 | ||
|RCA clean | |RCA clean. | ||
|Before Si deposition in LPCVD furnace, the quartz (fused silica) wafers need to be cleaned | |Before Si deposition in LPCVD furnace, the quartz (fused silica) wafers need to be cleaned | ||
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]] | |[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]] | ||
| Line 38: | Line 45: | ||
|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.2 | !1.2 | ||
|Low-Pressure Chemical Vapour Deposition (LPCVD) of Si | |Low-Pressure Chemical Vapour Deposition (LPCVD) of Si. | ||
|LPCVD deposition of 300 nm amorphous Si | |LPCVD deposition of 300 nm amorphous Si | ||
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]]. | |[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]]. | ||
| Line 46: | Line 53: | ||
|- | |- | ||
!1.3 | !1.3 | ||
|Si anisotropic wet etch | |Si anisotropic wet etch. | ||
|Removal of the Si from the back side of the wafer. | |Removal of the Si from the back side of the wafer. | ||
| [[Specific_Process_Knowledge/Etch/KOH_Etch|KOH]]. | | [[Specific_Process_Knowledge/Etch/KOH_Etch|KOH]]. | ||
| Line 55: | Line 62: | ||
|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.4 | !1.4 | ||
|Plasma surface treatment | |Plasma surface treatment. | ||
|To ensure that all organic remainings are gone, wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | |To ensure that all organic remainings are gone, wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | ||
| | | | ||
| Line 67: | Line 74: | ||
|- | |- | ||
!1.5 | !1.5 | ||
|E-Beam Lithography (EBL) | |E-Beam Lithography (EBL). | ||
|Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure. | |Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure. | ||
| | | | ||
[[Specific_Process_Knowledge/Lithography/EBeamLithography/ | [[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOL_9500_User_Guide|JEOL JBX-9500 Electron-beam]] | ||
<br clear="all" /> | <br clear="all" /> | ||
|[[image:Image2_ebeam_on_Si.jpg|250x350px|center]] | |[[image:Image2_ebeam_on_Si.jpg|250x350px|center]] | ||
| Line 78: | Line 85: | ||
|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.6 | !1.6 | ||
|Advanced Silicon Etching | |Advanced Silicon Etching. | ||
|Creating sacrificial silicon template. | |Creating sacrificial silicon template. | ||
| | | | ||
| Line 88: | Line 95: | ||
|- | |- | ||
!1.7 | !1.7 | ||
|Scanning Electron Microscopy inspection | |Scanning Electron Microscopy inspection. | ||
|The fabricated template inspects by SEM | |The fabricated template inspects by SEM | ||
| | | | ||
| Line 104: | Line 111: | ||
|- style="background:#BCD4E6; color:black" | |- style="background:#BCD4E6; color:black" | ||
!1.8 | !1.8 | ||
|Plasma surface treatment | |Plasma surface treatment. | ||
|To ensure that all organic remainings are gone, template is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | |To ensure that all organic remainings are gone, template is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | ||
| | | | ||
| Line 117: | Line 124: | ||
|- | |- | ||
!1.9 | !1.9 | ||
|Atomic Layer Deposition (ALD) of TiO<sub>2</sub> | |Atomic Layer Deposition (ALD) of TiO<sub>2</sub>. | ||
|Deposition carried at 150C.Thickness is approx. 90 nm. | |Deposition carried at 150C.Thickness is approx. 90 nm. | ||
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] . | ||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] . | ||
| Line 136: | Line 143: | ||
|- | |- | ||
!1.11 | !1.11 | ||
|Scanning Electron Microscopy inspection | |Scanning Electron Microscopy inspection. | ||
|SEM inspection of ALD deposition and IBE etching. | |SEM inspection of ALD deposition and IBE etching. | ||
| | | | ||
| Line 159: | Line 166: | ||
|- | |- | ||
!1.13 | !1.13 | ||
|Scanning Electron Microscopy inspection | |Scanning Electron Microscopy inspection. | ||
|Proof of final result. | |Proof of final result. | ||
| | | | ||