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LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions

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'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/LabAdviser/Technology_Research/Fabrication_of_Hyperbolic_Metamaterials_using_Atomic_Layer_Deposition/TiO2_Q_plates click here]'''
<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br>
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br>
The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br></i>
====Procces flow description====
====Procces flow description====


The substrates for the samples were fabricated by depositing 1 μm of Si<sub>3</sub>N<sub>4</sub> (the resonator layer) on 100 mm silicon < 100 > wafers using low-pressure chemical vapor deposition. The process was carried out at 780C with ammonia (NH<sub>3</sub>) and dichlorosilane (SiH<sub>2</sub>Cl<sub>2</sub>) as reactive gases. Thickness and refractive index of the deposited silicon nitride was measured and confirmed using spectroscopic ellipsometry. The deposited Si<sub>3</sub>N<sub>4</sub> film was carefully analyzed for existence of cracks, particles and other defects using dark field optical microscopy. The best-quality wafer with Si<sub>3</sub>N<sub>4</sub> was selected and cleaved in pieces, which were used as substrates for the deposition of Al<sub>2</sub>O<sub>3</sub>/TiO<sub>2</sub> multilayers. Before inserting each substrate into the ALD reactor, it was placed on a Si carrier wafer. Therefore the Al<sub>2</sub>O<sub>3</sub>/TiO<sub>2</sub> multilayers were grown not only on the Si<sub>3</sub>N<sub>4</sub> layer but also on the dummy carrier wafer. After the ALD process was completed, the dummy was cleaved and its cross-section was characterized using scanning electron microscopy (SEM). The SEM images reveal high-quality homogeneous, conformal coatings, as seen in the examples in Figs 1. Such a method of deposited multilayers characterization turned out to be more feasible than the direct SEM characterization of multilayers on Si<sub>3</sub>N<sub>4</sub>, since the latter suffers from issues related to charge accumulation on the silicon nitride.
A 500 μm thick wafer of silica (SiO<sub>2</sub>) goes through RCA clean and low-pressure chemical vapor deposition (LPCVD) (furnace from Tempress) based on SiH<sub>4</sub> (silane) at 560<sup></sup>C to form a layer of 300 nm of amorphous silicon (Si) [Fig. 1]. The back side of deposited Si was etched using KOH wet etch. In order to remove residues from the etching process, it was performed oxygen plasma cleaning. A CSAR resist was spin-coated to the thickness of 150 nm, followed by exposure of Electron Beam Lithography (EBL) (JEOL JBX-9500 Electron-beam) generating a mask with concentric ring patterns. After development, the wafer was submitted to advanced silicon etch (ASE). To form the trenches of the TiO<sub>2</sub> structures, a thin film of TiO<sub>2</sub> was deposited using the ALD technique in a hot-wall system (Picosun R200), working with 2000 cycles at 150<sup></sup>C [Fig.1]. The precursors used were titanium tetrachloride (TiCl<sub>4</sub>) and H<sub>2</sub>O (supplied by Strem Chemicals Equipment). The process was followed by Ar<sup>+</sup> ion beam etching (IBE) on both sides of the wafer to remove excess of ALD deposited material. At the top most TiO<sub>2</sub> layer the physical sputtering of the sample using Ar<sup>+</sup> ions was performed in order to get access to Si core. On the backside, the Ar<sup>+</sup> ions were used to remove the deposited TiO<sub>2</sub>. Finally, we performed a reactive ion etch on silicon, leaving only the TiO<sub>2</sub> structures. The final system comprehends a base of SiO<sub>2</sub> with nano-structures of TiO<sub>2</sub> on it. Figure 2 shows the image of the system taken using scanning electron microscope (SEM) and conventional optical microscope. Figure 3 illustrates SEM cross-sectional image of the prepared Q-plate .




<gallery caption="" widths="1000px" heights="600px" perrow="1">
<gallery caption="" widths="1000px" heights="600px" perrow="1">
image:Q_plates_fab__sheme.jpg| High aspect ratio Al<sub>2</sub>O<sub>3</sub> and TiO<sub>2</sub> nanogratings.
image:Q_plates_fab_sheme_new.jpg| Figure 1. Scheme of fabrication flow.
</gallery>
</gallery>


<gallery caption="" widths="1000px" heights="600px" perrow="2">
<gallery caption="" widths="1000px" heights="600px" perrow="2">
image:TiO2nanorings.jpg| High aspect ratio Al<sub>2</sub>O<sub>3</sub> and TiO<sub>2</sub> nanogratings.
image:TiO2nanorings.jpg| Figure 2. TiO<sub>2</sub> concentric nanorings acting as a Q-plate. Insets show optical and SEM images of the whole plate.
image:Q_plates_cross_section.jpg| High aspect ratio Al<sub>2</sub>O<sub>3</sub> and TiO<sub>2</sub> nanogratings.
image:Q_plates_cross_section.jpg| Figure 3. Cross-sectional SEM image of the TiO<sub>2</sub> Q-plate. a) The low magnification image shows the whole plate b) High magnification allows to inspect individual rings cross-sections.
</gallery>
</gallery>


== Process flow ==
== Process flow ==
Hej Evgeniy <br>
Description of steps for fabrication of Q-plates.
Jeg har lagt dette eksemple på et process flow ind. Alt tekst og billeder skal selvfølgelig erstattes af relevante process steps for denne artikel.
 
Mvh. Berit


{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
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|-
|-
!1.1
!1.1
|Plasma surface treatment
|RCA clean.
|To ensure clean surface, the 100 mm Si wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|Before Si deposition in LPCVD furnace, the quartz (fused silica) wafers need to be cleaned
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]]
|[[image:00_zero (1)_nanogratings.JPG|250x350px|center|]]
|[[image:Zero1.jpg|250x350px|center|]]
|-
|-


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|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.2
!1.2
|DUV Resist patterning
|Low-Pressure Chemical Vapour Deposition (LPCVD) of Si.
|DUV
|LPCVD deposition of 300 nm amorphous Si
|[[Specific_Process_Knowledge/Lithography/DUVStepperLithography|DUV Stepper Lithography]].  
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]].  
|[[image:00_zero (2)_nanogratings.JPG|250x350px|center|]]
|[[image:Zero2.jpg|250x350px|center|]]
|-
|-


|-
|-
!1.3
!1.3
|Deep reactive ion etching (DRIE)
|Si anisotropic wet etch.
|DRIE; [[Specific_Process_Knowledge/Etch/DRIE-Pegasus/DUVetch|Recipe: PolySOI10]]
|Removal of the Si from the back side of the wafer.
| [[Specific_Process_Knowledge/Etch/DRIE-Pegasus|DRIE Pegasus]].
| [[Specific_Process_Knowledge/Etch/KOH_Etch|KOH]].
|[[image:00_zero (3)_nanogratings.JPG|250x350px|center|]]
|[[image:Image1_Si_on_SiO2.jpg|250x350px|center|]]
|-
|-


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|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.4
!1.4
|Plasma surface treatment
|Plasma surface treatment.
|To ensure that remainings of DUV resist are gone, samples are treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|To ensure that all organic remainings are gone, wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]].
|
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]]
<br clear="all" />
|
|
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|-
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|-
|-
!1.5
!1.5
|Scanning Electron Microscopy inspection
|E-Beam Lithography (EBL).
|By cleaving the sample it is possible to inspect DRIE etched Si trenches in cross-sectional mode
|Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure.
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
[[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOL_9500_User_Guide|JEOL JBX-9500 Electron-beam]]  
<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
|[[image:Image2_ebeam_on_Si.jpg|250x350px|center]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:Si_trenches_nanogratings.jpg|250x350px|center]]
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.6
!1.6
|Atomic Layer Deposition of either Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub>
|Advanced Silicon Etching.
|Deposition carried at 150C.Thickness is 90 nm.
|Creating sacrificial silicon template.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipes used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/Al2O3_deposition_using_ALD#Al2O3_recipe_for_deposition_on_high_aspect_ratio_structures| Al2O3T]] and [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] .
|
|[[image:00_zero (4)_nanogratings.JPG|250x350px|center]]
[[Specific_Process_Knowledge/Etch/ASE_(Advanced_Silicon_Etch)|ASE]]  
<br clear="all" />
|[[image:Image3_ASE_of_SI.jpg|250x350px|center]]
|-
|-


|-
|-
!1.7
!1.7
|Scanning Electron Microscopy inspection
|Scanning Electron Microscopy inspection.
|By cleaving the sample it is possible to inspect ALD coatings deposited on Si trenches in cross-sectional mode
|The fabricated template inspects by SEM
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
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<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_coating_nanogratings.jpg|250x350px|center]]  
|[[image:Si_template_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.8
!1.8
|Opening of deposited Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> top layers.
|Plasma surface treatment.
|Etching happens using ICP Metal etcher with Cl<sub>2</sub>/BCl<sub>3</sub> process gasses.
|To ensure that all organic remainings are gone, template is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].
|
|[[image:00_zero (6)_nanogratings.JPG|250x350px|center]]
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]]
<br clear="all" />
|
|-
|-


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|-
|-
!1.9
!1.9
|Scanning Electron Microscopy inspection
|Atomic Layer Deposition (ALD) of TiO<sub>2</sub>.
|By cleaving the sample it is possible to inspect ICP etcher results Si trenches in cross-sectional mode
|Deposition carried at 150C.Thickness is approx. 90 nm.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] .
|[[image:Image4_ALD_of_SI_template.jpg|250x350px|center]]
|-
 
 
|-
|- style="background:#BCD4E6; color:black"
!1.10
|Ion Beam Etching (IBE).
|Opening of deposited TiO<sub>2</sub> top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching.
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:Image5_ALD_Ar_sputtering.jpg|250x350px|center]]
|-
 
 
|-
!1.11
|Scanning Electron Microscopy inspection.
|SEM inspection of ALD deposition and IBE etching.
|
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]  
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<br clear="all" />
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_top_removal_nanogratings.jpg|250x350px|center]]  
|[[image:top_removal_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|-
|- style="background:#BCD4E6; color:black"
|- style="background:#BCD4E6; color:black"
!1.10
!1.12
|Selective etch of Si between ALD Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> coatings.
|Selective etch of Si between ALD TiO<sub>2</sub> coatings. (Reactive Ion Etching)
|Si etching proceeds using ICP Metal etcher with isotropic process based on SF<sub>f</sub> process gas.
|Si etching proceeds using Reactive Ion Etching (RIE) with isotropic process based on SF<sub>6</sub> process gas.
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].  
||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]].  
|[[image:00_zero (7)_nanogratings.JPG|250x350px|center]]
|[[image:Image6_ALD_Final_structure.jpg|250x350px|center]]
|-
|-




|-
|-
!1.11
!1.13
|Scanning Electron Microscopy inspection of fabricated structure.
|Scanning Electron Microscopy inspection.
|Proof of final result.
|Proof of final result.
|
|
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<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_grating_nanogratings.jpg|250x350px|center]]  
|[[image:Si_removal_q_plates.jpg|250x350px|center]]  
|-
|-


|-
|- style="background:#BCD4E6; color:black"
!1.12
|Ion beam etching. (Optional)
|Additional shape of the top part. 20 mijn etch using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage shoud be placed to 0<sup>o</sup> degree. SEM cross section is used for inspection
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:image1004_nanogratings.jpg|250x350px|center]]
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|-
|-
|}
|}
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