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[[Image:jbx9500.jpg|500x500px|thumb|JEOL JBX-9500 E-beam writer positioned in room E-2]]
'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Lithography/EBeamLithography click here]'''


'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch) click here]'''
Content and illustration by Thomas Pedersen, DTU Nanolab unless otherwise noted.


The JEOL JBX-9500 electron beam lithography system is a spot electron beam type lithography system designed for writing patterns with dimensions from nanometers to sub-micrometers. The minimum electron beam is around 5 nm, the maximum writitng field without stitching is 1 mm x 1 mm.
[[Category: Equipment |Lithography exposure]]
[[Category: Lithography|Exposure]]
<div class="keywords" style="display:none;">ebl e-beam writer e-beamwriter ebeamwriter e-beamlithography</div>


The machine is located in a class 10 cleanroom (E-2) with tight temperature and moisture control. The room must only be entered when the machines or equipment inside the room is intended to be used.
[[File:TPE02803.jpg|right|600px]]


You can read more about electron beam writing in this book published by [http://www.cnf.cornell.edu/cnf_spietoc.html SPIE].
=Quick links=
[[Specific Process Knowledge/Lithography/EBeamLithography/JEOLRequest|Exposure slot request]]


'''The user manual, technical information and contact information can be found in LabManager and LabAdviser:'''
[[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOL 9500 User Guide|JEOL 9500 User Guide]]
<!-- remember to remove the type of documents that are not present -->


<!-- give the link to the equipment info page in LabManager: -->
[[Specific_Process_Knowledge/Lithography/EBeamLithography/FirstEBL|My first JEOL 9500 exposure tutorial]]
# [http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=292  E-beam writer in LabManager]
# [[Specific_Process_Knowledge/Lithography/EBeamLithography/JBX9500Manual|User manual for JBX-9500 e-beam writer on LabAdviser]]
# [[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|BEAMER Manual on LabAdviser]]
# [[Specific_Process_Knowledge/Lithography/EBeamLithography/FilePreparation|Sdf- and jdf file preparation manual on LabAdviser]]


[[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOLAlignment|Alignment exposure]]


=Performance of the e-beam writers at DTU Danchip=
[[Specific_Process_Knowledge/Lithography/EBeamLithography/Cassettes|JEOL cassette specifications]]


[[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|Beamer guide]]


{| border="2" cellspacing="0" cellpadding="10" width="60%"
[[Specific_Process_Knowledge/Lithography/EBeamLithography/TRACER|Tracer guide]]
|-
!style="background:silver; color:black;" align="left"|Purpose
|style="background:LightGrey; color:black"|pattern an electron sensitive resist
|style="background:WhiteSmoke; color:black"|Mainly for pattering structures with minimum feature size between 12 nm - 1 µm
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Performance
|style="background:LightGrey; color:black"|Resolution
|style="background:WhiteSmoke; color:black"|
* ~5 nm beam diameter, ~10 nm lines obtained in 50 nm thick resist (CSAR)
 
|-
|style="background:LightGrey; color:black"|Maximum writing area without stitching
|style="background:WhiteSmoke; color:black"|
*1mm x 1mm
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="6"|Process parameter range
|style="background:LightGrey; color:black"|E-beam voltage
|style="background:WhiteSmoke; color:black"|
*100kV
|-
|style="background:LightGrey; color:black"|Scanning speed
|style="background:WhiteSmoke; color:black"|
*100MHz
|-
|style="background:LightGrey; color:black"|Min. electron beam size
|style="background:WhiteSmoke; color:black"|
*5nm
|-
|style="background:LightGrey; color:black"|Min. step size
|style="background:WhiteSmoke; color:black"|
*1nm
|-
|style="background:LightGrey; color:black"|Beam current range
|style="background:WhiteSmoke; color:black"|
*0.1nA to 60nA in normal conditions (see available condition files <span class="plainlinks">[http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=log&mach=292&type=status here]</span>)
|-
|style="background:LightGrey; color:black"|Dose range
|style="background:WhiteSmoke; color:black"|
*0.001µC/cm<sup>2</sup> to 100000µC/cm<sup>2</sup>
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Samples
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
Wafer cassettes:
*6 x 2" wafers
*2 x 4" wafers
*1 x 6" wafer
*Special wafer cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D).
|-
| style="background:LightGrey; color:black"|Substrate material allowed
|style="background:WhiteSmoke; color:black"|
*Silicon, quartz, pyrex, III-V materials
*Wafers with layers of silicon oxide or silicon (oxy)nitride
*Wafers with layers of metal


|}
[[Specific Process Knowledge/Lithography/EBeamLithography/EBLProcessExamples|EBL process examples]]


[[Specific_Process_Knowledge/Lithography/EBeamLithography/Dose_Testing|Dose testing setups for JEOL 9500]]


<br clear="all" />
= Introduction to E-beam lithography at DTU Nanolab =


= Getting started =
DTU Nanolab has two E-beam writing systems, a JEOL JBX-9500 FSZ and a Raith eLINE Plus. The two systems are very different and new users should consult the EBL team to dertermine which system is appropriate for a particular project or type of sample. The general specifications of the two tools are given in the table below and may serve as a guideline for choice of system to use, especially the pros and cons list at the end of the table. Newcommers to EBL should start by watching our '''[https://youtu.be/2bFUO201DS4 JEOL 9500 process video]''' to see how a typical process is done.


<span style="font-size: 90%; text-align: right;">[[Specific_Process_Knowledge/Lithography/EBeamLithography#top|Go to top of this page]]</span>


[[Image:Conversion.png|600px|right|]]
Compared to UV lithography EBL is somewhat more complicated and in general a significantly longer process. Writing time (per area) is much higher and thus EBL is only adviseable for structures with Critical Dimensions (CD) below 1 µm. For CD equal to or higher than 1 µm please consider our '''[[Specific_Process_Knowledge/Lithography/UVExposure#Aligner:_Maskless_02 | Maskless Aligner tools.]]'''


To request for an e-beam training session, contact [mailto:e-beam@danchip.dtu.dk e-beam@danchip.dtu.dk]; a DTU Danchip personnel will hereafter provide a time slot. Users require '''at least 4 training sessions''' before being allowed full acccess to the machine. The first training will focus on file preparation and compilation alone.


== Getting started and training in E-Beam Lithography ==
The JEOL 9500 system has a fairly steep learning curve and the information below and corresponding links are fairly comprehensive and describes uses and options that first time users of the JEOL 9500 system should not venture into. Instead, first time users of the JEOL 9500 system should consult our dedicated [[Specific Process Knowledge/Lithography/EBeamLithography/FirstEBL|My First JEOL 9500 Exposure guide]] which showcases a JEOL 9500 job from start to finish in a tutorial form.


'''It takes several months to get full authorization to the machine. Therefore, if you are either in a hurry, or a visiting researcher, or only require a few e-beam exposures to fulfill your project, let one of your authorized colleagues expose for you.'''
Please request training in E-Beam lithography by sending an email with your process flow to [mailto:training@nanolab.dtu.dk training@nanolab.dtu.dk].


==EBL staff at DTU Nanolab==
Questions related to E-beam lithography should be directed to the EBL staff.


{| class="wikitable"
|-
|[[File:thope.png|150px]] || [[File:pxshi.png|150px]] || [[File:elelop.png|150px]] || [[File:meenadh.png|150px]]
|-
|[mailto:thope@dtu.dk Thomas Pedersen]
JEOL 9500 & Raith E-Line
|| [mailto:pxshi@dtu.dk Peixiong Shi]
JEOL 9500
|| [mailto:elelop@dtu.dk Elena Lopez Aymerich]
JEOL 9500
|| [mailto:meenadh@dtu.dk Meena Dhankhar]
Raith E-Line
|}


Before you request for a training on the machine, fulfill the following steps:
== JEOL 9500 and Raith eLine Plus specifications ==


'''Prepare a v30-file:'''
{| border="2" cellspacing="0" cellpadding="10" width="60%"


# Prepare your pattern using a layout software (L-edit, CleWin, CAD) and export that to GDS format. Check your GDS-file by importing it in e.g. <span class="plainlinks">[http://www.wieweb.com/ns6/index.html CleWin]</span> or L-edit. In order to reach the files from the computers inside the cleanroom it is recommended to either dropbox them or send them per email to yourself.
!colspan="4" border="none" style="background:silver; color:black;" align="center"|EBL system comparison table
# Convert the GDS file to v30 using BEAMER; a manual for BEAMER software is found [[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|here]]
|-
 
'''Create sdf and jdf-files:'''
 
#download [http://download.cnet.com/SuperEdi/3000-2352_4-10291091.html SuperEdi],
#read the sdf and jdf-file manual found [[Specific_Process_Knowledge/Lithography/EBeamLithography/FilePreparation|here]],
#find templates of sdf and jdf files on the cleanroom drive in the folder E-beam sdf and jdf templates.
 
''' Gather Experience '''
 
#Assist a fully trained colleague of yours when she or he e-beam writes, gather as much knowledge about your e-beam run, i.e. which e-beam current, aperture and dose to use, which shot pitch (e.g. SHOT A,10).
# Study the logbook for the e-beam writer: sheet 1 gives you an overview of which condition files (currents and apertures) have been in use recently by which user on which type of resist. On sheet 2 in this logbook you can find a writing time estimation program.
# Study the manual for the machine, it can be found [[Specific_Process_Knowledge/Lithography/EBeamLithography/JBX9500Manual|here]]
 
<br clear="all" />
 
== General Rules ==
 
For safety reasons, even fully trained users are only authorized to mount substrates into the e-beam cassettes, but not authorized to load the cassettes into the autoloader.
To use the e-beam writer, book the machine via LabManager, '''note the number and type of substrate as well as the condition file to be used in the 'Public Comment:' field in LabManager'''. Mount your substrate in the cassette and pre-align if necessary. Call for help from DTU Danchip staff to load your cassette into the robot loader (the autoloader).
 
After your exposure, fully trained users can unload their cassettes from the autoloader, unmount their substrates and re-load an '''empty''' cassette into the autoloader.
If you are unable to unmount your substrates before another user requires the cassette, you must accept that either the next user or DTU Danchip personel unmount your substrates.


= E-beam resists and Process Flows =
!colspan="2" border="none" style="background:silver; color:black;" align="center"|Equipment
 
|style="background:silver; color:black;" align="left"|'''JEOL JBX-9500FSZ'''
<span style="font-size: 90%; text-align: right;">[[Specific_Process_Knowledge/Lithography/EBeamLithography#top|Go to top of this page]]</span>
|style="background:silver; color:black;" align="left"|'''[[Specific_Process_Knowledge/Lithography/EBeamLithography/eLINE|Raith eLINE Plus]]'''
 
 
The table describes the e-beam resist used in the cleanroom for standard e-beam exposure. Some of resists are not provided by DTU Danchip and some are not yet approved for common use in the cleanroom and are currently being tested. If you wish to test some of these resists or other resists, please contact [mailto:lithography@danchip.dtu.dk Lithography].
 
Standard DTU Danchip resists purchased and tested by DTU Danchip:
 
{|border="1" cellspacing="1" cellpadding="3" style="text-align:left;" width="95%"
|-
|-


!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Performance
|style="background:LightGrey; color:black"|Resolution
|style="background:WhiteSmoke; color:black"|8 nm
|style="background:WhiteSmoke; color:black"|35 nm
|-
|-
|-style="background:silver; color:black"
|'''Resist'''
|'''Polarity'''
|'''Manufacturer'''
|'''Comments'''
|'''Technical reports'''
|'''Spin Coater'''
|'''Thinner'''
|'''Developer'''
|'''Rinse'''
|'''Remover'''
|'''Process flows (in docx-format)'''


|style="background:LightGrey; color:black"|Maximum writing field
|style="background:WhiteSmoke; color:black"|1mm x 1mm
|style="background:WhiteSmoke; color:black"|1mm x 1mm
|-
|-


!style="background:silver; color:black" align="left" valign="top" rowspan="6"|Process parameter range
|style="background:LightGrey; color:black"|Acceleration voltage
|style="background:WhiteSmoke; color:black"|100 kV
|style="background:WhiteSmoke; color:black"|1-30 kV
|-
|-
|-style="background:WhiteSmoke; color:black"
|'''[[Specific_Process_Knowledge/Lithography/CSAR|CSAR]]'''
|Positive
|[http://www.allresist.com AllResist]
|Standard positive resist, very similar to ZEP520.
|[[media:Allresist_CSAR62_English.pdf‎|Allresist_CSAR62_English.pdf‎]],, [[media:CSAR_62_Abstract_Allresist.pdf‎|CSAR_62_Abstract_Allresist.pdf‎]]
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|Anisole
|AR-600-546, AR-600-548, N50, MIBK:IPA
|IPA
|AR-600-71, 1165 Remover
|[[media:Process_Flow_CSAR.docx‎|Process Flow CSAR.docx‎]] <br> [[media:Process Flow CSAR ESPACER.docx|Process Flow CSAR with ESPACER]] <br> [[media:Process Flow CSAR with Al.docx|Process Flow CSAR with Al]]


|style="background:LightGrey; color:black"|Scan speed
|style="background:WhiteSmoke; color:black"|200 MHz
|style="background:WhiteSmoke; color:black"|20 MHz
|-
|-
|-style="background:LightGrey; color:black"
|'''[[Specific_Process_Knowledge/Lithography/ZEP520A|ZEP520A]]'''
|Positive resist, contact [mailto:Lithography@danchip.dtu.dk Lithography] if you plan to use this resist
|ZEON
|Positive resist
|[[media:ZEP520A.pdf|ZEP520A.pdf]], [[media:ZEP520A.xls|ZEP520A spin curves on SSE Spinner]]
|[[Specific_Process_Knowledge/Lithography/Coaters#SSE Spinner|SSE]], [[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|Anisole
|ZED-N50/Hexyl Acetate,n-amyl acetate, oxylene. [[media:JJAP-51-06FC05.pdf‎|JJAP-51-06FC05.pdf‎]], [[media:JVB001037.pdf‎|JVB001037.pdf‎]]
|IPA
|acetone/1165
|[[media:Process_Flow_ZEP.docx|Process_Flow_ZEP.docx]]


|style="background:LightGrey; color:black"|Min. electron beam size
|style="background:WhiteSmoke; color:black"|4 nm
|style="background:WhiteSmoke; color:black"|10 nm
|-
|-
|-style="background:WhiteSmoke; color:black"
|'''[[Specific_Process_Knowledge/Lithography/ARP617|Copolymer AR-P 617]]'''
|Positive
|AllResist
|Approved, not tested yet. Used for trilayer (PEC-free) resist-stack or double-layer lift-off resist stack. Please contact [mailto:Lithography@danchip.dtu.dk Lithography] for information.
|[[media:AR_P617.pdf‎|AR_P617.pdf‎]]
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|PGME
|AR 600-55, MIBK:IPA
|
|acetone/1165
|Trilayer stack: [[media:Process_Flow_Trilayer_Ebeam_Resist.docx‎|Process_Flow_Trilayer_Ebeam_Resist.docx‎]]


|style="background:LightGrey; color:black"|Min. step size
|style="background:WhiteSmoke; color:black"|0.25 nm
|style="background:WhiteSmoke; color:black"|1 nm
|-
|-
|-style="background:WhiteSmoke; color:black"
|'''[[Specific_Process_Knowledge/Lithography/mrEBL6000|mr EBL 6000.1]]'''
|Negative
|[http://http://www.microresist.de/home_en.htm MicroResist]
|Standard negative resist
|[[media:mrEBL6000 Processing Guidelines.pdf‎|mrEBL6000 processing Guidelines.pdf‎]]
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|Anisole
|mr DEV
|IPA
|mr REM
|[[media:Process_Flow_mrEBL6000.docx‎|Process_Flow_mrEBL6000.docx‎]]


|style="background:LightGrey; color:black"|Beam current range
|style="background:WhiteSmoke; color:black"|0.1 nA to 100 nA
|style="background:WhiteSmoke; color:black"|0.01 to 12 nA
|-
|-
|-style="background:LightGrey; color:black"
|'''HSQ (XR-1541)'''
|Negative
|DOW Corning
|Approved. Standard negative resist, mainly for III-V materials
|
|[[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|
|TMAH, AZ400K:H2O
|H2O
|
|


|style="background:LightGrey; color:black"|Minimum dwell time
|style="background:WhiteSmoke; color:black"| 5 ns
|style="background:WhiteSmoke; color:black"| 50 ns
|-
|-
|-style="background:LightGrey; color:black"
|'''AR-N 7520'''
|Negative
|AllResist
|Both e-beam, DUV and UV-sensitive resist. Currently being tested, contact [mailto:pxshi@danchip.dtu.dk Peixiong Shi] for information.
|[[media:AR-N7500-7520.pdf‎|AR-N7500-7520.pdf‎]]
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|PGMEA
|AR 300-47, TMAH
|H2O
|
|


 
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Samples
|}
|style="background:LightGrey; color:black"|Batch size
 
|style="background:WhiteSmoke; color:black"|
 
Wafer cassettes:
Non-standard DTU Danchip resists not purchased by DTU Danchip:
*6 x 2" wafers
 
*2 x 4" wafers
{|border="1" cellspacing="1" cellpadding="3" style="text-align:left;" width="95%"
*1 x 6" wafer
*1 x 8" wafer
*Special chip cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D).
|style="background:WhiteSmoke; color:black"|
*Chips up to 75 x 75 mm
*4" wafer holder
*6" wafer holder (stage movement limited to central 100 x 100 mm region)
|-
|-


|style="background:LightGrey; color:black"|Substrate material allowed
|style="background:WhiteSmoke; color:black"|
*Silicon, quartz, pyrex, III-V materials
*Wafers with layers of silicon oxide or silicon (oxy)nitride
*Wafers with layers of metal
|style="background:WhiteSmoke; color:black"|
*Silicon, quartz, pyrex, III-V materials
*Wafers with layers of silicon oxide or silicon (oxy)nitride
*Wafers with layers of metal
|-
|-
|-style="background:silver; color:black"
|'''Resist'''
|'''Polarity'''
|'''Manufacturer'''
|'''Comments'''
|'''Technical reports'''
|'''Spinner'''
|'''Thinner'''
|'''Developer'''
|'''Rinse'''
|'''Remover'''
|'''Process flows (in docx-format)'''


!style="background:silver; color:black" align="left" valign="top" rowspan="2"|General considerations
|style="background:LightGrey; color:black"|Pros
|style="background:WhiteSmoke; color:black"|
*100 kV
*Sub 10 nm resolution
*Automatic beam optimization
*High current and process speed
*Automatic sample exchange
*High level of programmability for automatic job execution
*EBL workhorse for large designs
|style="background:WhiteSmoke; color:black"|
*Readily available
*More intuitive software
*Easier SEM mode alignment
*Build in SEM automation for post exposure process control
*2D stacks (HBN/graphene) allowed without Al coating
*Excellent for small chips or small area design exposure
|-
|-


|style="background:LightGrey; color:black"|Cons
|style="background:WhiteSmoke; color:black"|
*Steep learning curve
*Availability - booking calendar is usually full 5 weeks ahead
|style="background:WhiteSmoke; color:black"|
*Maximum 30 kV
*User dependent performance/beam optimization
*Minimum feature size >35 nm
*Difficult to handle design files >1 GB
*Slower writing speed


|}


=Fundementals of EBL pattern writing=
==Electron exposure==
An E-beam writing system utilizes a focused electron beam to expose an electron sensitive resist in order to define a pattern on a substrate. For a positive tone resist the electron beam will scission polymer bonds within the resist to increase the dissolution rate when the substrate is placed in a developer solution. In this way the exposed part of the resist can be dissolved while maintaining the unexposed resist on the substrate. For a negative resist the electron beam will make the resist less soluble and hence the unexposed resist can be removed with a developer.


 
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
|-
|-style="background:LightGrey; color:black"
| [[image:PositiveNegative.png|700px]]
|'''PMMA'''
|-
|Positive
| colspan="1" style="text-align:center;|
|
Exposure and development result of a positive resist (left) and a negative resist (right).
|We have various types of PMMA in the cleanroom, none are provided by DTU Danchip. Please contact [mailto:Lithography@danchip.dtu.dk Lithography] for information.
|
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]  
|
|MIBK:IPA (1:3), IPA:H2O
|IPA
|acetone/1165/Pirahna
|
 
 
|-
|-style="background:WhiteSmoke; color:black"
|'''ZEP7000'''
|Positive
|ZEON
|Not approved. Low dose to clear, can be used for trilayer (PEC-free) resist-stack. Please contact [mailto:Lithography@danchip.dtu.dk Lithography] for information.
|[[media:ZEP7000.pdf|ZEP7000.pdf]]
|[[Specific_Process_Knowledge/Lithography/Coaters#Manual Spinner 1|Manual Spinner 1 (Laurell)]], [[Specific_Process_Knowledge/Lithography/Coaters#Spin_coater:_Manual_Labspin|Spin Coater Labspin]]
|
|ZED-500/Hexyl Acetate,n-amyl acetate, oxylene.
|IPA
|acetone/1165
|Trilayer stack: [[media:Process_Flow_Trilayer_Ebeam_Resist.docx‎|Process_Flow_Trilayer_Ebeam_Resist.docx‎]]
 
|}
|}




<br/>
In order to define a pattern in the resist enough electrons have to be supplied to the exposed area, i.e. the exposure dose has to be sufficiently high. The area exposure dose is expressed in units of µC/cm<sup>2</sup>. The dose to clear the resist (for a positive resist) can be obtained from a contrast curve such as the one below. Dose to clear varies a lot between different resist types and is also dependent on processing parameters such as
<br/>
<br/>


= Cassettes =
*Acceleration voltage
*Resist thickness
*Developer agent and concentration
*Post exposure baking


Authorized users are allowed to unload a cassette from the robot loader (autoloader) and mount their substrate but '''not''' allowed to load the cassette into the loader after mount.


We have one chip cassette, 2 2" cassettes, 2 4" cassettes, many 6" cassettes and 1 8" cassette. Some cassettes are made of Aluminum, others of Titanium. The thermal expansion coefficient of Ti is much lower than of Al; bear this in mind if you have crucial patterns to expose.  
In general it is always advisable to do a dose test of the pattern one intends to define to experimentally establish the optimum dose. For more information on resist dose please refer to the [[Specific Process Knowledge/Lithography/EBeamLithography/EBLsubstratePrep| EBL substrate preparation guide.]]


'''Keep''' an eye on the wafer orientation when you mount; the 2" aluminum cassette still have wafer orientation flat-up.




{| cellpadding="2" style="border: 2px solid darkgray;" align="right"
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
! width="250" |
|-
! width="250" |
| [[image:ContrastCurvesCSAR March2016 log.png|600px]]
! width="250" |
|-
! width="250" |
| colspan="1" style="text-align:center;|
! width="250" |
Contrast curve for AR-P 6200 exposed at 100 kV with the JEOL 9500 exposure system. Illustration: Tine Greibe.
|- border="0"
| [[File:IMG_0239.jpg|150px]]
|[[File:IMG_6440.jpg|150px]] [[File:IMG_6441.jpg|150px]]
| [[File:IMG_6433.jpg|150px]]  [[File:IMG_6434.jpg|150px]]
| [[File:IMG_6436.jpg|150px]] [[File:IMG_6437.jpg|150px]]
|[[File:IMG_6438.jpg|150px]]  [[File:IMG_6439.jpg|150px]]
|- align="center"
| chip Al/Cu cassette with slot widths of 20 mm, 12 mm, 8 mm and 4 mm || 2" Ti cassette; wafer orientation is flat-down || 2" Al cassette; wafer orientation is flat-up || 4" Ti cassette; wafer orientation is flat-down || 4" Al cassette; wafer orientation is flat-down
 
|}
|}


==Writing principle==
Both of our EBL systems lets the user define a desired area dose to expose the resist with. Based on the beam current the systems will then calculate the necessary beam dwell to achieve the requested dose in the drawn areas. It is always the drawn (filled) parts of a pattern that will get exposed. In addition to area dose the Raith eLine tool allows the user to define a line dose for exposure of single lines. The JEOL 9500 system does not allow that.


<br> <br> <br> <br>
Before the pattern is exposed onto the substrate the pattern is broken down (fractured) into simple trapezoids and each trapezoidal shape is filled with beam shots, i.e. individual beam positions that together will make up the pattern. This is illustrated below with a simple pattern consisting of a square. The actual beam spot size is dependent on beam current and the pitch between beam positions is (within certain limitations) defined by the user.


= Alignment of exposure to existing pattern on wafer =


If you need to align an exposure to an existing pattern on a wafer you need wafer marks (or global marks) to align your exposure to. If you are exposing chips (i.e. many small GDS-files you repeat in a matrix), chip marks is recommended to align every chip.
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
 
|-
'''Please note that manual alignment (using the SEM) is not allowed.''' You should use semi-automatic alignment only. In rare cases where semi-automatic alignment is impossible, you should remove the resist around the wafer marks before loading the wafer/chip into the machine.
| [[image:EBLBeamShots.png|200px]]
 
|-
{| cellpadding="2" style="border: 2px solid darkgray;" align="right"
| colspan="1" style="text-align:center;|
! width="200" |
Simple shape filled in with beam shots.
! width="200" |
! width="300" |
! width="300" |
|- border="0align="center"
| [[File:mark example2.png|100px]]
| [[File:GlobalMark.png|120px]]
| [[File:P Q marks and chip marks.png|250px]]
| [[File:Chip example.png|150px]]
|- align="center"
| Definition of length and width of global mark, use L = 500-1000 µm, W 3-5 µm || Text around mark not recommended || Global mark (P and Q) positions on wafer. Positions of global marks are entered in jdf file using wafer coordinate system. || Example of chip with 4 chip marks. Always position the chip marks outside the chip pattern. Position of chip marks are entered in jdf file using chip coordinate system, i.e. center of chip is (0,0).
|}
|}


'''1 Material:''' Global marks or chip marks should be clearly visible in a 100keV SEM, i.e. preferably defined by Ti/Au or another 'heavy' metal, alternatively the wafer marks should be etched. In Si, etched mark should be around 1 µm deep in order to be detectable by the machine. Shallow etched (even 200 nm etched profiles) global marks or global marks in Si or marks defined by a light metal as Al can be hard to locate manually as well as automatically by the machine.


'''2 Design: '''
The electron source is continuously emitting electrons and exposure of the beam towards the sample is controlled by a beam blanker. The position of the beam is controlled by the beam deflector and scanning coils. The pattern is written one beam shot at a time in a serial process as this
* Global marks: You need at least two wafer marks, a P mark and a Q mark. It is recommended to have many P and Q marks available on the wafer to choose from. The x-coordinate of the P mark should be smaller than the x-coordinate of the Q mark. The global marks should either be crosses or L-shaped, they should be as narrow as possible and 500 - 1000 microns in length. If the wafer contains a number of identical marks, the marks should be marked in order to identify the 'right' alignment mark (the scan width of the SEM is 1 mm x 1 mm). Text around the wafer mark is NOT recommended. Wafer marks formed as crosses with lengths of 1000 microns and 3-5 microns in width are recommended.
* Chip marks: Prepare 1 or 4 chip marks on every chip. The chip marks can be smaller than global marks, as only very fine alignment is performed with chip marks. The chip marks should either be crosses or L-shaped and text around the marks is NOT recommended.


#Beam positioning for 1st beam position of current trapezoidal shape
#Unblank the beam
##Exposure
##Reposition for next beam shot
#Blank the beam at end of trapezoidal shape


<br> <br>
Steps 2.1 and 2.2 continues in a loop until all beam shots of the current trapezoidal shape has been executed after which the beam is blanked and the system moves on to the next trapezoidal shape. It is obvious that exposure in such a way is relatively slow and has an overhead on top of the actual exposure time since time is also spent on beam positioning and blanking/unblanking the beam.


== Field stitching ==
==Exposure grid and exposure field==
In this experiment, several writing fields (1 mm x 1 mm) were stitched together. Vernier scales on the edges of each writing field shows the field stitching bewteen fields.
Both systems have a maximum writing field size of 1000 x 1000 µm<sup>2</sup> since the deflection of the beam is limited to ±500 µm in both x- and y-direction. Patterns inside a writing filed is written by beam deflection only and hence the substrate stage remains stationary. Geometry larger than a single writing field will be fractured across multiple writing fields and hence between fields the substrate stage will move to reposition the substrate directly under the column as illustrated below.


 
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
{|border="1" cellspacing="0" cellpadding="3" style="text-align:left;"  style="width: 95%"
|-
|-
 
| [[image:EBLFields.png|600px]]
|-
|-  
|-style="background:Black; color:White"
| colspan="1" style="text-align:center;|
!colspan="6"|wafer 11.17 Stitching accuracy, Processed by TIGRE, April 2015
Illustration of a waveguide spanning four exposure fields. Between fields the stage will reposition the substrate below the column.
|-
 
|-
|-style="background:WhiteSmoke; color:black"
!Resist
!E-beam exposure
!Development
!Metallisation
!Lift-off
!Characterisation
|-
 
|-
|-style="background:WhiteSmoke; color:black"
|CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC
|JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L1: 1st set of Vernier scales on edges (North, Upper Right, East, Lower Right, South, Lower Left, West, Upper Left) of entire writi9ng field
|AR-600-546, 60 s
|5 nm Ti, 45 nm Au, Wordentec (D-2)
|AR-600-71, 5-10 min, 4s ultrasonic (D-3)
|Zeiss Supra 60VP, 10kV, Inlens detector
|-
 
|}
|}


If neighbouring writing fields are not properly aligned features fractured across multiple writing fields may suffer from stitching errors, i.e. pattern discontinuities where the patterns do not align properly to each other. On the JEOL system write field alignment is ensured by a fully automated calibration sequence using internal alignment features. This ensures field stitching usually on the order of 10-15 nm or less. On the Raith system write field alignment is performed on the users own substrate and accuracy can vary.


The beam shots described above are placed onto the systems exposure grid, hence the resolution of beam shot placement is governed by the exposure grid. The resolution of this grid is determined by the positioning DAC of the system, on the JEOL 9500 this is 20 bit and on the Raith eLine it is 16 bit. Hence the JEOL 9500 system has in principle 2<sup>20</sup> = 1.048.576 grid positions along each axis while the Raith system has 2<sup>16</sup> = 65.384 grid positions along each axis. This means the JEOL system can maintain a 1 nm exposure grid over the entire 1000 x 1000 µm<sup>2</sup> writing field whereas the Raith tool will have a 16 nm exposure grid at the maximum writing field.


[[File:FieldToField.png|700px]]


==Beam pitch, beam current and exposure dose relationship==
A sample is exposed at a certain beam current. On the JEOL system this is selectable (in certain discrete steps) while on the Raith tool the beam current is bound by the choice of acceleration voltage and aperture. The user will input an area dose for the resist to be exposed with and the system will calculate the shot time (dwell time) of the beam to provide the requested dose. It is clear that high doses will require long dwell times whereas low doses will require short dwell times for the same beam current. There is however another important parameter to the dwell time calculation and that is the beam/shot pitch, i.e. how far beam shots are placed from each other. The beam scanner on the JEOL 9500 system is 100 MHz, thus the temporal resolution is 10 ns and it is not possible to have a beam shot (or dwell time) less than 10 ns. The Raith system has a 20 MHz beam scanner and hence the minimum shot time is 50 ns. This, in combination with beam current and exposure dose will set a lower limit on the beam pitch.


<br> <br>
The relation might not be obvious at first and is illustrated below. The two identical features are filled with beam shots at two different pitches. the right version has a lower beam pitch (half of the other) and thus there are simply many more beam shots. Consequently, to provide the same area exposure dose the shot time for the right side feature will be much shorter. At half the pitch there will be four times the number of beam shots and thus the shot time will be 1/4 the shot time of the left feature.


== Overlay accuracy (layer to layer stitching) ==
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
| [[image:BeamPitch.png|500px]]
|-
| colspan="1" style="text-align:center;|
Example feature filled with beam shots at one times beam diameter (left) and half beam diameter (right).
|}


In this experiment, a set of Vernier marks (L1) were exposed along with global marks and chip marks in appr 170 nm CSAR. This layer was developed, metalized and lift-off. A new layer of resist (appr 170 nm CSAR) was spin coated onto the wafer. A second set of Vernier marks (L2) was aligned to two gloabl marks and 4 chip marks and exposed. Layer 2 was developed, metalized and lift-off. The final pattern SEM inspected in Zeiss Supra 60VP.
The shot time can be calculated as ''t = D·p<sup>2</sup>/I'', where ''D'' is the dose in µC/cm<sup>2</sup>, ''p'' is beam pitch and ''I'' is current. As a practical example let us consider an exposure at 2 nA beam current and a desired dose of 250 µC/cm<sup>2</sup>. At 4 nm beam pitch the shot time will come out to 20 ns, while at 2 nm beam pitch it will come out at 5 ns and thus violate the hardware limitation of 10 ns for the JEOL system. In order to expose the pattern with 2 nm shot pitch one would have to choose a lower beam current at the expense of increased writing time.


The shot time is in fact such an important number that both systems will tell the user what it is. On the JEOL system the shot time is displayed in a table after job compilation, see below. On the Raith tool it is indicated in the '''Patterning Parameter Calculation''' box, see below.


{|border="1" cellspacing="0" cellpadding="3" style="text-align:left;"  style="width: 95%"
|-


{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;"
|-
|-
|-style="background:Black; color:White"
| <pre>
!colspan="6"|wafer 11.17 Stitching accuracy, Processed by TIGRE, April 2015
Start estimation writing time  -----
|-
Shot counting start -----
  thopeQU23008a.v30                                              at 11-MAR-2023 14:53:40
Shot counting end -----


|-
  Seq.  writing time    shottime[nsec]  resist[uC/cm2]  stdcur[nA]  scanstep
|-style="background:WhiteSmoke; color:black"
  1        0:52:27            16.000          200.000        2.000        16
!Resist
  2        0:13:46            13.500          200.000      12.000        36
!E-beam exposure
  3         0:11:15            12.000          100.000      12.000        48
!Development
  4        0:12:10           13.500          200.000      12.000        36
!Metallisation
  5         0:11:14            12.000          100.000      12.000        48
!Lift-off
Total :    1:40:51
!Characterisation
|-
 
|-
|-style="background:WhiteSmoke; color:black"
|CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC
|JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L1: 1st set of Vernier scales, 6 global marks and 4 chip marks in every chip
|AR-600-546, 60 s
|5 nm Ti, 45 nm Au, Wordentec (D-2)
|AR-600-71, 5-10 min, 4s ultrasonic (D-3)
|
|-
 
|-
|-style="background:WhiteSmoke; color:black"
|CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC
|JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L2: 2nd set of Vernier scales aligned to 2 global marks and 4 chip marks in every chip (scan width 10 µm)
|AR-600-546, 60 s
|5 nm Ti, 45 nm Au, Wordentec (D-2)
|AR-600-71, 5-10 min, 4s ultrasonic (D-3)
|Zeiss Supra 60VP, 10kV, Inlens detector
|-


Estimation result file : thopeQU23008a.csv
End estimation writing making time    -----
</pre> || [[image:eLine_dose.PNG|600px]]
|-
| colspan="2" style="text-align:center;|
Shot time as calculated by the JEOL system (left) and Raith eLine system (right).
|}
|}


==Exposure time==
E-beam exposure is a serial writing process and the writing time (t) will scale with dose (D), area (A) and beam current (I) as:
t = D*A/I


The Vernier scales were distributed over the entire writing field: C = center, UR/LR/LL/UL = Upper/Lower Right/Left, MN/ME/MS/MW = Middle North/East/South/West.
It is thus essential to find the right balance between the area that needs to be defined and a beam current that will provide sufficient pattern fidelity and quality. During pattern writing the tool will also use time on cyclic calibration and stage movement as defined by the job path and pattern layout. The exposure time can be estimated based on the [[:File:Writing Time Estimator.xlsx|Writing Time Estimator Excel sheet]].
 
 
[[File:LayerToLayer1.png|700px]]
 
[[File:LayerToLayer2.png|700px]]
 
 
<br clear="all" />
 
<br> <br>
 
= Proximity Error Correction =
 
 
<span style="font-size: 90%; text-align: right;">[[Specific_Process_Knowledge/Lithography/EBeamLithography#top|Go to top of this page]]</span>
 


Even though the electron beam diameter is below 5 nm, the feature and pitch resolution in resist is limited by the forward and backward scattering of the electrons. The forward scattering depends on the electron acceleration voltage, the resist material and thickness. The backward scattering depends on the electron acceleration voltage and the substrate material [http://en.wikipedia.org/wiki/Electron-beam_lithography], [http://en.wikipedia.org/wiki/Proximity_effect_%28electron_beam_lithography%29].
= Exposure information =
== Generalized workflow ==
While the EBL workflow resembles that of UV lithography there are a few additional complications and the parameter space is somewhat larger. The complications all arise from using electrons rather than light for exposure. Since a beam of electrons is used for exposure the substrate must be sufficiently conductive and grounded in order not to build up a charge. If the substrate in itself is not conductive a thin metal film or other conductive surface layer must be applied to it, read more on this in the resist section. Another complication is secondary exposure from backscattered electrons. This is a much bigger topic and covered in the pattern preparation section. A generalised workflow is shown below.


As the travel distance of backscattered electrons is fairly large, e-beam patterned structures will be influenced by adjacent e-beam patterned structures, i.e. a proximity effect. These proximity effects can be avoided either by simulating a proximity error correction (PEC) in BEAMER or by using the right stack of e-beam resist.
[[File:EBLWorkflow.png|1200px|frameless|center|alt=Generalized EBL workflow.|Generalized EBL workflow.]]


Since substrate preparation and development processes are (nearly) identical for the JEOL and Raith eLine systems they are described in common below. Pattern preparation, job preparation and job execution are fairly different between the two tools and hence these steps are described on the specific tool pages.


== Proximity Error Correction (PEC) in BEAMER ==
== Substrate preparation and resist information==
Substrates must be prepared for EBL by applying an e-beam sensitive resist and possibly a discharge layer. Please consult the EBL substrate preparation guide on how to prepare your substrate and to find resist information.


[[Image:beamer5.jpg|frame|250x250px|right]]
*[[Specific Process Knowledge/Lithography/EBeamLithography/EBLsubstratePrep| EBL substrate preparation guide]]


BEAMER is endowed with a software that corrects for proximity errors in the e-beam exposure. You can read more about this function in the BEAMER manual [[Specific_Process_Knowledge/Lithography/EBeamLithography/BEAMER|here]] and in the BEAMER presentation here [[media:BEAMERPresentation.pdf‎|BEAMERPresentation.pdf‎]].
== Pattern preparation ==
Pattern preparation is somewhat different depending on if a pattern is exposed on JEOL 9500 or Raith eLine Plus. Please refer to the correct pattern preparation section below.


The proximity error correction require a forward and a backward range parameter, alfa and beta, and a ratio of backscattered energy to the forward scattered energy, eta. As alfa depends on the electron acceleration voltage, which is constant at 100kV, alfa is in BEAMER fixed to 0.007. Help to find beta and eta can be found [http://nanolithography.gatech.edu/proximity.htm here].
[[Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation|Pattern preparation for exposure on JEOL 9500.]]


Alternatively, a [http://en.wikipedia.org/wiki/Proximity_effect_%28electron_beam_lithography%29 point-spread function] can be used in BEAMER to calculate the optimised dose-variation.
[[Specific Process Knowledge/Lithography/EBeamLithography/RaithPatternPreparation|Pattern preparation for exposure on Raith eLine Plus.]]


== Job preparation ==
Job preparation is also different depending on if a pattern is exposed on JEOL 9500 or Raith eLine Plus. Please refer to the correct job preparation section below.


<br clear="all" />
[[Specific Process Knowledge/Lithography/EBeamLithography/JEOLJobPreparation|Job preparation for exposure on JEOL 9500.]]


== Trilayer resist stack ==
[[Specific Process Knowledge/Lithography/EBeamLithography/RaithJobPreparation|Job preparation for exposure on Raith eLine Plus.]]
As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [http://avspublications.org/jvst/resource/1/jvstal/v19/i4/p1304_s1]. This reists stack has not yet been tested at DTU Danchip. A process flow for this procedure can be found here [[media:Process_Flow_Trilayer_Ebeam_Resist.docx‎|Process_Flow_Trilayer_Ebeam_Resist.docx‎]], but please contact [mailto:Lithography@danchip.dtu.dk Lithography] before use.


== Job execution ==
Job execution is very different between the JEOL and Raith systems. The procedures are described on their respective user guide pages:


<br clear="all" />
*[[Specific Process Knowledge/Lithography/EBeamLithography/JEOL 9500 User Guide|Job execution on JEOL 9500]]
*[https://labmanager.dtu.dk/d4Show.php?id=18413&mach=445 Raith eLine Plus user manual]


= Charging of non-conductive substrates=
== Development ==


<span style="font-size: 90%; text-align: right;">[[Specific_Process_Knowledge/Lithography/EBeamLithography#top|Go to top of this page]]</span>
AR 600-546 and ZED N-50 developers are available in a semi automatic puddle developer [[Specific_Process_Knowledge/Lithography/Development#Developer:_E-beam|Developer: E-beam]] in E-4, mainly intended for development of AR-P 6200 and ZEP 520A. It has automatic recipes for puddle development cycles for 10, 30 and 60 seconds of either of the two developers, each finishing off with an IPA rinse and drying cycle. The system can handle chips, 2", 4" and 6" wafers.


All substrates are grounded to the cassette when properly loaded. In a non-conducting substrate, the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist.


If you wish to investigate the charge dissipation using other methods than below, please contact [mailto:lithography@danchip.dtu.dk Lithography].
Other resist have to be developed in the E-beam developer fumehood in E-4 in beakers. Please notice there are specific beaker sets for alkaline developers and for solvent based developers.


== ESPACER ==
== Post development inspection ==
After development it is often necesarry to evaluate the result by SEM to verify feature dimensions. This can conviently be done in the Raith eLine Plus tool which apart from being an EBL tool is also a semiautomatic SEM. The strong suit of the tool is the ability to link/align a design file to the substrate and simply define image positions in the design file. The user can then set up a long list of image locations and the tool will acquire the SEM images without further user input. When set up correctly the system can acquire about one image per 5 seconds which is very advantageous for large arrays of structures. For an introduction to this, please refer to our [https://youtu.be/YoZF_6FeVb4 automatic SEM introduction video.]


Espacer is a chemical that works as a discharging layer; it is spun onto the wafer on top of the resist and easily rinsed off the wafer after e-beam exposure. Visit this page for more information: [[Specific_Process_Knowledge/Lithography/Espacer|Espacer]]


After image acquisition the images can be semi automatically processed with ProSEM to determine feature sizes. For large image sets the software can generate an Excel sheet with various dimension outputs.


== Aluminum coating ==
=EBL process examples=
Process examples and results can be found [[Specific Process Knowledge/Lithography/EBeamLithography/EBLProcessExamples|on this page.]]


At DTU Danchip, we recommend to use a thin (20 nm) layer of thermally evaporated [[Specific Process Knowledge/Thin film deposition/Deposition of Aluminium|aluminum]] on top of the e-beam resist. Preferably, the thickness of Al and the e-beam dose should be optimised to the features you wish to e-beam pattern [http://nedds.co.uk/wp-content/uploads/2013/06/Greer-et-al-DRM-29-July-2012.pdf]. A good starting point is 20 nm Al; from here dose and development can be optimised to reach the resolution and feature size required.
= Literature on E-beam Lithography =


The process flow for a standard e-beam exposure on ZEP520 with Al on top can be found here [[media:Process_Flow_ZEP_with_Al.docx‎|Process_Flow_ZEP_with_Al.docx‎]].
* Handbook of Microlithography, Micromachining, and Microfabrication, Volume 1: Microlithography, P. Rai-Choudhury (Editor), chapter 2 (p 139 – 250). Link to book can be found here: http://www.cnf.cornell.edu/cnf_spietoc.html
* Lithography, Wiley, 2011: Chapter 3, Electron Beam Lithography by Stefan Landis: http://onlinelibrary.wiley.com/doi/10.1002/9781118557662.ch3/summary

Latest revision as of 12:47, 26 June 2024

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Content and illustration by Thomas Pedersen, DTU Nanolab unless otherwise noted.

Quick links

Exposure slot request

JEOL 9500 User Guide

My first JEOL 9500 exposure tutorial

Alignment exposure

JEOL cassette specifications

Beamer guide

Tracer guide

EBL process examples

Dose testing setups for JEOL 9500

Introduction to E-beam lithography at DTU Nanolab

DTU Nanolab has two E-beam writing systems, a JEOL JBX-9500 FSZ and a Raith eLINE Plus. The two systems are very different and new users should consult the EBL team to dertermine which system is appropriate for a particular project or type of sample. The general specifications of the two tools are given in the table below and may serve as a guideline for choice of system to use, especially the pros and cons list at the end of the table. Newcommers to EBL should start by watching our JEOL 9500 process video to see how a typical process is done.


Compared to UV lithography EBL is somewhat more complicated and in general a significantly longer process. Writing time (per area) is much higher and thus EBL is only adviseable for structures with Critical Dimensions (CD) below 1 µm. For CD equal to or higher than 1 µm please consider our Maskless Aligner tools.


Getting started and training in E-Beam Lithography

The JEOL 9500 system has a fairly steep learning curve and the information below and corresponding links are fairly comprehensive and describes uses and options that first time users of the JEOL 9500 system should not venture into. Instead, first time users of the JEOL 9500 system should consult our dedicated My First JEOL 9500 Exposure guide which showcases a JEOL 9500 job from start to finish in a tutorial form.

Please request training in E-Beam lithography by sending an email with your process flow to training@nanolab.dtu.dk.

EBL staff at DTU Nanolab

Questions related to E-beam lithography should be directed to the EBL staff.

Thomas Pedersen

JEOL 9500 & Raith E-Line

Peixiong Shi

JEOL 9500

Elena Lopez Aymerich

JEOL 9500

Meena Dhankhar

Raith E-Line

JEOL 9500 and Raith eLine Plus specifications

EBL system comparison table
Equipment JEOL JBX-9500FSZ Raith eLINE Plus
Performance Resolution 8 nm 35 nm
Maximum writing field 1mm x 1mm 1mm x 1mm
Process parameter range Acceleration voltage 100 kV 1-30 kV
Scan speed 200 MHz 20 MHz
Min. electron beam size 4 nm 10 nm
Min. step size 0.25 nm 1 nm
Beam current range 0.1 nA to 100 nA 0.01 to 12 nA
Minimum dwell time 5 ns 50 ns
Samples Batch size

Wafer cassettes:

  • 6 x 2" wafers
  • 2 x 4" wafers
  • 1 x 6" wafer
  • 1 x 8" wafer
  • Special chip cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D).
  • Chips up to 75 x 75 mm
  • 4" wafer holder
  • 6" wafer holder (stage movement limited to central 100 x 100 mm region)
Substrate material allowed
  • Silicon, quartz, pyrex, III-V materials
  • Wafers with layers of silicon oxide or silicon (oxy)nitride
  • Wafers with layers of metal
  • Silicon, quartz, pyrex, III-V materials
  • Wafers with layers of silicon oxide or silicon (oxy)nitride
  • Wafers with layers of metal
General considerations Pros
  • 100 kV
  • Sub 10 nm resolution
  • Automatic beam optimization
  • High current and process speed
  • Automatic sample exchange
  • High level of programmability for automatic job execution
  • EBL workhorse for large designs
  • Readily available
  • More intuitive software
  • Easier SEM mode alignment
  • Build in SEM automation for post exposure process control
  • 2D stacks (HBN/graphene) allowed without Al coating
  • Excellent for small chips or small area design exposure
Cons
  • Steep learning curve
  • Availability - booking calendar is usually full 5 weeks ahead
  • Maximum 30 kV
  • User dependent performance/beam optimization
  • Minimum feature size >35 nm
  • Difficult to handle design files >1 GB
  • Slower writing speed

Fundementals of EBL pattern writing

Electron exposure

An E-beam writing system utilizes a focused electron beam to expose an electron sensitive resist in order to define a pattern on a substrate. For a positive tone resist the electron beam will scission polymer bonds within the resist to increase the dissolution rate when the substrate is placed in a developer solution. In this way the exposed part of the resist can be dissolved while maintaining the unexposed resist on the substrate. For a negative resist the electron beam will make the resist less soluble and hence the unexposed resist can be removed with a developer.

Exposure and development result of a positive resist (left) and a negative resist (right).


In order to define a pattern in the resist enough electrons have to be supplied to the exposed area, i.e. the exposure dose has to be sufficiently high. The area exposure dose is expressed in units of µC/cm2. The dose to clear the resist (for a positive resist) can be obtained from a contrast curve such as the one below. Dose to clear varies a lot between different resist types and is also dependent on processing parameters such as

  • Acceleration voltage
  • Resist thickness
  • Developer agent and concentration
  • Post exposure baking


In general it is always advisable to do a dose test of the pattern one intends to define to experimentally establish the optimum dose. For more information on resist dose please refer to the EBL substrate preparation guide.


Contrast curve for AR-P 6200 exposed at 100 kV with the JEOL 9500 exposure system. Illustration: Tine Greibe.

Writing principle

Both of our EBL systems lets the user define a desired area dose to expose the resist with. Based on the beam current the systems will then calculate the necessary beam dwell to achieve the requested dose in the drawn areas. It is always the drawn (filled) parts of a pattern that will get exposed. In addition to area dose the Raith eLine tool allows the user to define a line dose for exposure of single lines. The JEOL 9500 system does not allow that.

Before the pattern is exposed onto the substrate the pattern is broken down (fractured) into simple trapezoids and each trapezoidal shape is filled with beam shots, i.e. individual beam positions that together will make up the pattern. This is illustrated below with a simple pattern consisting of a square. The actual beam spot size is dependent on beam current and the pitch between beam positions is (within certain limitations) defined by the user.


Simple shape filled in with beam shots.


The electron source is continuously emitting electrons and exposure of the beam towards the sample is controlled by a beam blanker. The position of the beam is controlled by the beam deflector and scanning coils. The pattern is written one beam shot at a time in a serial process as this

  1. Beam positioning for 1st beam position of current trapezoidal shape
  2. Unblank the beam
    1. Exposure
    2. Reposition for next beam shot
  3. Blank the beam at end of trapezoidal shape

Steps 2.1 and 2.2 continues in a loop until all beam shots of the current trapezoidal shape has been executed after which the beam is blanked and the system moves on to the next trapezoidal shape. It is obvious that exposure in such a way is relatively slow and has an overhead on top of the actual exposure time since time is also spent on beam positioning and blanking/unblanking the beam.

Exposure grid and exposure field

Both systems have a maximum writing field size of 1000 x 1000 µm2 since the deflection of the beam is limited to ±500 µm in both x- and y-direction. Patterns inside a writing filed is written by beam deflection only and hence the substrate stage remains stationary. Geometry larger than a single writing field will be fractured across multiple writing fields and hence between fields the substrate stage will move to reposition the substrate directly under the column as illustrated below.

Illustration of a waveguide spanning four exposure fields. Between fields the stage will reposition the substrate below the column.

If neighbouring writing fields are not properly aligned features fractured across multiple writing fields may suffer from stitching errors, i.e. pattern discontinuities where the patterns do not align properly to each other. On the JEOL system write field alignment is ensured by a fully automated calibration sequence using internal alignment features. This ensures field stitching usually on the order of 10-15 nm or less. On the Raith system write field alignment is performed on the users own substrate and accuracy can vary.

The beam shots described above are placed onto the systems exposure grid, hence the resolution of beam shot placement is governed by the exposure grid. The resolution of this grid is determined by the positioning DAC of the system, on the JEOL 9500 this is 20 bit and on the Raith eLine it is 16 bit. Hence the JEOL 9500 system has in principle 220 = 1.048.576 grid positions along each axis while the Raith system has 216 = 65.384 grid positions along each axis. This means the JEOL system can maintain a 1 nm exposure grid over the entire 1000 x 1000 µm2 writing field whereas the Raith tool will have a 16 nm exposure grid at the maximum writing field.


Beam pitch, beam current and exposure dose relationship

A sample is exposed at a certain beam current. On the JEOL system this is selectable (in certain discrete steps) while on the Raith tool the beam current is bound by the choice of acceleration voltage and aperture. The user will input an area dose for the resist to be exposed with and the system will calculate the shot time (dwell time) of the beam to provide the requested dose. It is clear that high doses will require long dwell times whereas low doses will require short dwell times for the same beam current. There is however another important parameter to the dwell time calculation and that is the beam/shot pitch, i.e. how far beam shots are placed from each other. The beam scanner on the JEOL 9500 system is 100 MHz, thus the temporal resolution is 10 ns and it is not possible to have a beam shot (or dwell time) less than 10 ns. The Raith system has a 20 MHz beam scanner and hence the minimum shot time is 50 ns. This, in combination with beam current and exposure dose will set a lower limit on the beam pitch.

The relation might not be obvious at first and is illustrated below. The two identical features are filled with beam shots at two different pitches. the right version has a lower beam pitch (half of the other) and thus there are simply many more beam shots. Consequently, to provide the same area exposure dose the shot time for the right side feature will be much shorter. At half the pitch there will be four times the number of beam shots and thus the shot time will be 1/4 the shot time of the left feature.

Example feature filled with beam shots at one times beam diameter (left) and half beam diameter (right).

The shot time can be calculated as t = D·p2/I, where D is the dose in µC/cm2, p is beam pitch and I is current. As a practical example let us consider an exposure at 2 nA beam current and a desired dose of 250 µC/cm2. At 4 nm beam pitch the shot time will come out to 20 ns, while at 2 nm beam pitch it will come out at 5 ns and thus violate the hardware limitation of 10 ns for the JEOL system. In order to expose the pattern with 2 nm shot pitch one would have to choose a lower beam current at the expense of increased writing time.

The shot time is in fact such an important number that both systems will tell the user what it is. On the JEOL system the shot time is displayed in a table after job compilation, see below. On the Raith tool it is indicated in the Patterning Parameter Calculation box, see below.


Start estimation writing time   -----
Shot counting start -----
  thopeQU23008a.v30                                               at 11-MAR-2023 14:53:40
Shot counting end -----

  Seq.   writing time    shottime[nsec]   resist[uC/cm2]   stdcur[nA]   scanstep 
   1         0:52:27            16.000          200.000        2.000         16
   2         0:13:46            13.500          200.000       12.000         36
   3         0:11:15            12.000          100.000       12.000         48
   4         0:12:10            13.500          200.000       12.000         36
   5         0:11:14            12.000          100.000       12.000         48
 Total :     1:40:51

Estimation result file : thopeQU23008a.csv
End estimation writing making time     -----

Shot time as calculated by the JEOL system (left) and Raith eLine system (right).

Exposure time

E-beam exposure is a serial writing process and the writing time (t) will scale with dose (D), area (A) and beam current (I) as: t = D*A/I

It is thus essential to find the right balance between the area that needs to be defined and a beam current that will provide sufficient pattern fidelity and quality. During pattern writing the tool will also use time on cyclic calibration and stage movement as defined by the job path and pattern layout. The exposure time can be estimated based on the Writing Time Estimator Excel sheet.

Exposure information

Generalized workflow

While the EBL workflow resembles that of UV lithography there are a few additional complications and the parameter space is somewhat larger. The complications all arise from using electrons rather than light for exposure. Since a beam of electrons is used for exposure the substrate must be sufficiently conductive and grounded in order not to build up a charge. If the substrate in itself is not conductive a thin metal film or other conductive surface layer must be applied to it, read more on this in the resist section. Another complication is secondary exposure from backscattered electrons. This is a much bigger topic and covered in the pattern preparation section. A generalised workflow is shown below.

Generalized EBL workflow.
Generalized EBL workflow.

Since substrate preparation and development processes are (nearly) identical for the JEOL and Raith eLine systems they are described in common below. Pattern preparation, job preparation and job execution are fairly different between the two tools and hence these steps are described on the specific tool pages.

Substrate preparation and resist information

Substrates must be prepared for EBL by applying an e-beam sensitive resist and possibly a discharge layer. Please consult the EBL substrate preparation guide on how to prepare your substrate and to find resist information.

Pattern preparation

Pattern preparation is somewhat different depending on if a pattern is exposed on JEOL 9500 or Raith eLine Plus. Please refer to the correct pattern preparation section below.

Pattern preparation for exposure on JEOL 9500.

Pattern preparation for exposure on Raith eLine Plus.

Job preparation

Job preparation is also different depending on if a pattern is exposed on JEOL 9500 or Raith eLine Plus. Please refer to the correct job preparation section below.

Job preparation for exposure on JEOL 9500.

Job preparation for exposure on Raith eLine Plus.

Job execution

Job execution is very different between the JEOL and Raith systems. The procedures are described on their respective user guide pages:

Development

AR 600-546 and ZED N-50 developers are available in a semi automatic puddle developer Developer: E-beam in E-4, mainly intended for development of AR-P 6200 and ZEP 520A. It has automatic recipes for puddle development cycles for 10, 30 and 60 seconds of either of the two developers, each finishing off with an IPA rinse and drying cycle. The system can handle chips, 2", 4" and 6" wafers.


Other resist have to be developed in the E-beam developer fumehood in E-4 in beakers. Please notice there are specific beaker sets for alkaline developers and for solvent based developers.

Post development inspection

After development it is often necesarry to evaluate the result by SEM to verify feature dimensions. This can conviently be done in the Raith eLine Plus tool which apart from being an EBL tool is also a semiautomatic SEM. The strong suit of the tool is the ability to link/align a design file to the substrate and simply define image positions in the design file. The user can then set up a long list of image locations and the tool will acquire the SEM images without further user input. When set up correctly the system can acquire about one image per 5 seconds which is very advantageous for large arrays of structures. For an introduction to this, please refer to our automatic SEM introduction video.


After image acquisition the images can be semi automatically processed with ProSEM to determine feature sizes. For large image sets the software can generate an Excel sheet with various dimension outputs.

EBL process examples

Process examples and results can be found on this page.

Literature on E-beam Lithography