Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch): Difference between revisions

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-'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/AOE_(Advanced_Oxide_Etch) click here]'''
+{{cc-nanolab}}
+'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/AOE_(Advanced_Oxide_Etch) click here]'''
+[[Category: Equipment|Etch AOE]]
+[[Category: Etch (Dry) Equipment|AOE]]
 == Etching using the dry etch technique AOE (Advanced oxide etch) ==
-[[Image:AOE.jpg|300x300px|thumb|AOE: positioned in cleanroom 2]]
+[[Image:AOE.jpg|300x300px|thumb|AOE: positioned in cleanroom B-1, {{photo1}}]]
-The AOE can be used for etching silicon oxide, silicon (oxy)nitride and quartz. Look in the manuals for the AOE to see how to operate the machine (you can find the manuals in LabManager on the AOE page).
+Name: M/PLEX ICP - AOE (Advanced Oxide Etcher) <br>
+Vendor: STS (now SPTS) <br>
+The AOE can be used for dry etching silicon oxide, silicon (oxy) nitride and quartz. Look in the manuals for the AOE to see how to operate the machine (you can find the manuals in LabManager on the AOE page).
+'''The user manual, quality control procedure and results, user APV, technical information and contact information can be found in LabManager:'''
+<!-- remember to remove the type of documents that are not present -->
+<!-- give the link to the equipment info page in LabManager: -->
+[http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=115  AOE in LabManager - requires login]
 == Process information ==
-*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE|Etch of Silicon Oxide using AOE]]
+*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE|Etch of Silicon Oxide]]
-*[[/Si etch using AOE|Si etch using AOE]]
+*[[/Si etch using AOE|Etch of Si]]
-*[[/Remove resist in the AOE|Remove resist in the AOE]]
+*[[/Remove resist in the AOE|Remove/etch resist/barc]]
-*[[/Quartz etch using AOE|Quartz etch using AOE]]
+*[[Specific Process Knowledge/Etch/Etching of Bulk Glass/AOE etching of fused silica|Etch of Fused Silica]]
-*[[/Silicon Nitride Etch using AOE|Silicon Nitride Etch using AOE]]
+*[[/Quartz etch using AOE|Etch of Quartz - special very thick samples]]
+*[[/Silicon Nitride Etch using AOE|Etch of Silicon Nitride]]
 ===Limitations using the AOE===
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 ====Transparent wafers====
-Transparent wafers are a challange for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test succesfully.
+Transparent wafers are a challenge for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test successfully.
-# The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer (could be aluminium).
+# The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer
-#The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transfering it into chamber or deposite a more conducting layer on the backside of the wafer. This could be aluminium but also 1-2µm P-Si may be enough.
+#The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transferring it into chamber or deposit a more conducting/semiconducting layer on the backside of the wafer (could be silicon, maybe Chromium, please ask). 1-2µm P-Si may be enough, maybe even less.
-==A rough overview of the performance of AOE and some process related parameters==
+==An overview of the performance of AOE and some process related parameters==
 {| border="2" cellspacing="0" cellpadding="10"
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 |style="background:LightGrey; color:black"|Etch rates
 |style="background:WhiteSmoke; color:black"|
-~0.2-0.6 µm/min
+~0.05-0.6 µm/min
 |-
 |style="background:LightGrey; color:black"|Anisotropy
@@ Line 46: / Line 61: @@
 *Typical profiles: 86-90 degrees
 |-
-!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Process parameter range
+!style="background:silver; color:black" align="left" valign="top" rowspan="4"|Process parameter range
 |style="background:LightGrey; color:black"|Process pressure
 |style="background:WhiteSmoke; color:black"|
-*~2-20 mTorr
+*~0.2-95 mTorr
+|-
+|style="background:LightGrey; color:black"|Process power
+|style="background:WhiteSmoke; color:black"|
+*Coil power: up to 3000W
+*Platen power: up to 600W
+|-
+|style="background:LightGrey; color:black"|Platen temperature
+|style="background:WhiteSmoke; color:black"|
+*-10 to 60 degrees Celcius
 |-
 |style="background:LightGrey; color:black"|Gas flows
 |style="background:WhiteSmoke; color:black"|
-*C<math>_4</math>F<math>_8</math>: 0-40 sccm
+*C<sub>4</sub>F<sub>8</sub>: 0-40 sccm
-*O<math>_2</math>: 0-100 sccm
+*O<sub>2</sub>: 0-100 sccm
-*CF<math>_4</math>: 0-100 sccm
+*CF<sub>4</sub>: 0-100 sccm
-*H<math>_2</math>: 0-30 sccm
+*H<sub>2</sub>: 0-30 sccm
 *He: 0-500 sccm
-*N<math>_2</math>: 0-1000 sccm
+*N<sub>2</sub>: 0-1000 sccm
-*SF<math>_6</math>: 0-300 sccm
+*SF<sub>6</sub>: 0-300 sccm
 |-
 !style="background:silver; color:black" align="left" valign="top" rowspan="3"|Substrates