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'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide click here]'''
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*[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]]
*[[Specific Process Knowledge/Etch/Wet Silicon Oxide Etch (BHF)|Wet Silicon Oxide Etch]]
*[[/SiO2 etch using ASE|SiO2 etch using ASE]]
 
*[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]]
*[[Specific_Process_Knowledge/Etch/III-V_RIE/III_V_RIE_ETCHES#CHF3.2FO2_etch |SiO2 etch using III-V RIE]]
*[[/SiO2 etch using AOE|SiO2 etch using AOE]]
*[[/SiO2 etch using AOE|SiO2 etch using AOE]]
*[[Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4|SiO2 etch with DRIE Pegasus 4]]
*[[/SiO2 etch using ASE|SiO2 etch using ASE]]
*[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]]
*[[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide|SiO2 etch using ICP metal]]
*[[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
*[[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
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![[Specific Process Knowledge/Etch/III-V RIE |III-V RIE]]
![[Specific Process Knowledge/Etch/III-V RIE |III-V RIE]]
![[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)|AOE (Advanced Oxide Etch)]]
![[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)|AOE (Advanced Oxide Etch)]]
![[Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4|DRIE Pegasus 4]]
![[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP metal]]
![[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP metal]]
![[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
![[Specific Process Knowledge/Etch/IBE&frasl;IBSD Ionfab 300|IBE/IBSD Ionfab 300]]
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*Isotropic etch
*Isotropic etch
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*Anisotropic etch: vertical sidewalls.
*Primarily for samples with small amounts of metals on.
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*Anisotropic etch: vertical sidewalls
*Anisotropic etch: vertical sidewalls
*Primarily for III-V samples
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*Anisotropic etch: vertical sidewalls
*Anisotropic etch: vertical sidewalls
*Premarily for III-V samples
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*Anisotropic etch: vertical sidewalls
*Anisotropic etch: almost vertical sidewalls
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*Anisotropic etch: almost vertical sidewalls
*Anisotropic etch: almost vertical sidewalls
*We prefer that SiO2 etch takes place in the AOE, since it is a very polymeric process an the ICP is not heating as much as the AOE.
*We prefer that SiO2 etch takes place in the AOE or Pegasus 4.
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*Primarily for pure physical etch by sputtering with Ar-ions
*Primarily for pure physical etch by sputtering with Ar-ions
*Also for slanted gratings
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*Gas phase HF etching with ethanol as carrier
*Gas phase HF etching with ethanol as carrier
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*Aluminium
*Aluminium
*Chromium (Please try to avoid this)
*Chromium (Please try to avoid this)
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*Photoresist
*DUV resist
*E-beam resist
*Si
*Silicon Nitride
*Chromium (ask for permission)
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*Photoresist
*Photoresist
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*Aluminium
*Aluminium
*Chromium
*Chromium
*Ti
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*Any material that is accepted in the machine
*Any material that is accepted in the machine
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*HF VPE mask material 1
*Aluminium
*HF VPE mask material 2
*Aluminium oxide
*HF VPE mask material 3
*Polysilicon
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|-


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*~75 nm/min (Thermal oxide) in BHF
*~75 nm/min (Thermal oxide) in BHF
*~90 nm/min (Thermal oxide) in SIO Etch
*~80 nm/min (Thermal oxide) in BOE 7:1 Etchant VLSI with Surfactant
*~25 nm/min (Thermal oxide) in 5%HF
*~25 nm/min (Thermal oxide) in 5%HF
*~6 nm/min (Thermal oxide) in 1%HF
*~3-4µm/min in 40%HF
*~3-4µm/min in 40%HF
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*Process dependent
*Process dependent
*Tested range: ~60nm/min - ~550nm/min
*Tested range: ~60nm/min - ~550nm/min
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*Process dependent
<500nm/min
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*Process dependent
*Process dependent
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*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 100 mm wafer
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)
*<nowiki>#</nowiki>1 150 mm wafers (only when the system is set up to 150mm)
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*As many small samples as can be bonded on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer bonded on a 150mm wafer
*<nowiki>#</nowiki>1 100 mm wafer bonded on a 150nm wafer
*<nowiki>#</nowiki>1 150 mm wafers
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*As many small samples as can be fitted on a 150mm wafer
*As many small samples as can be fitted on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer fitted on a 150mm wafer
*<nowiki>#</nowiki>1 50 mm wafer fittesd on a 150mm wafer
*<nowiki>#</nowiki>1 100 mm wafer fitted on a 150nm wafer
*<nowiki>#</nowiki>1 100 mm wafer fitted on a 150nm wafer
*<nowiki>#</nowiki>1 150 mm wafers
*<nowiki>#</nowiki>1 150 mm wafers
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*Aluminium
*Aluminium
*Chromium (try to avoid it)
*Chromium (try to avoid it)
*Quartz/fused silica
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*[http://labmanager.dtu.dk/function.php?module=XcMachineaction&view=edit&MachID=456 Please take a look in the cross contamination sheet in LabManager for details]
*Silicon
*Silicon Oxide
*Silicon Nitride
*Silicon Oxynitride
*Photoresist
*DUV resist
*E-beam resist
*Chromium
*Quartz/fused silica
*Quartz/fused silica
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<br clear="all" />
<br clear="all" />
==Dry etch with Hard mask==
''By Martin Lind Ommen - ''fall 2016'' '' <br>
Testing selectivities for SiO<sub>2</sub> etching with hard masks on AOE and ICP metal with different recipes.All tests are done with 100% etching load<br>
[[File:Dry etching by Martin Lind Ommen Fall 2016.png|600px]]<br>
MLO_psi is the version of SiO2_psi on labadviser that is shown under low line with reduction.<br>
The recipe ICP is on ICP metal call: A SiO2 etch with C4F8 with resist mask<br>
I had problems with this recipe - it gave polymer on the surface, therefor I do not have more info on that.<br>
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