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LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/AZO pillars: Difference between revisions

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DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers
4,346 edits
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image:AZO_tubes_fab_supplementary_eves.jpg| Figure 4. SEM verfication for each fabrication step of tube production. Left side shows cross-sectional images and right side of the Figure shows the top view of the structures.
image:AZO_tubes_fab_supplementary_eves.jpg| Figure 4. SEM verfication for each fabrication step of tube production. Left side shows cross-sectional images and right side of the Figure shows the top view of the structures.
</gallery>
</gallery>
== Process flow ==
Description of steps for fabrication of AZO nanopillars and tubes.
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-
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!1.1
|RCA.(Optional step. Needs only if SOI substrates requires)
|To ensure a clean surface before furnace processing, the wafers needs to be RCA cleaned.
|
[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]]
|[[image:1_zero1.jpg|250x350px|center|]]
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|-
|- style="background:#BCD4E6; color:black"
!1.2
|Thermal oxidation of Si.(Optional step. Needs only if SOI substrates requires)
|Creating 200 nm thin SiO2 layer using [[Specific_Process_Knowledge/Thermal Process/Oxidation|Dry Oxidation process]] in a C1 Furnace Anneal-oxide equipment.
|[[Specific_Process_Knowledge/Thermal_Process/C1_Furnace_Anneal-oxide|C1 Furnace Anneal-oxide]].
|[[image:2_zero2.jpg|250x350px|center|]]
|-
|-
!1.3
|LPCVD deposition of Si. (Optional step. Needs only if SOI substrates requires)
|LPCVD of amorphous silicon using [[Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_polysilicon/Deposition_of_polysilicon_using_LPCVD/Standard_recipes,_QC_limits_and_results_for_the_6"_polysilicon_furnace|AMORPOLY]] recipe in 6" Furnace LPCVD PolySilicon.
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" Furnace LPCVD PolySilicon]].
|[[image:3_1_SOI.jpg|250x350px|center|]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.4
|DUV Resist patterning.
|DUV
|[[Specific_Process_Knowledge/Lithography/DUVStepperLithography|DUV Stepper Lithography]].
|[[image:4_1_SOI_DUV.jpg|250x350px|center|]]
|-
|-
!1.3000000000000000000000000000
|Deep reactive ion etching (DRIE).
|DRIE; [[Specific_Process_Knowledge/Etch/DRIE-Pegasus/DUVetch|Recipe: PolySOI10]] Recipe needs to be tuned. Adjusted parameters: temperature, etching and passivation times.
| [[Specific_Process_Knowledge/Etch/DRIE-Pegasus|DRIE Pegasus]].
|[[image:00_zero (3)_nanogratings.JPG|250x350px|center|]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.4000000000000000000000000000000
|Plasma surface treatment.
|To ensure that remainings of DUV resist are gone, samples are treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]]
<br clear="all" />
|
|-
|-
!1.50000000000000000000000000000000
|Scanning Electron Microscopy inspection.
|By cleaving the sample it is possible to inspect DRIE etched Si trenches in cross-sectional mode.
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:Si_trench007.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.60000000000000000000000000000000000
|Atomic Layer Deposition of Al-doped ZnO (AZO).
|Deposition carried at 200<sup>o</sup>C. Thickness is above 100 nm.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/AZO_deposition_using_ALD| AZO 20T]].
|[[image:02_ALD_eves.jpg|250x350px|center]]
|-
|-
!1.700000000000000000000000000
|Scanning Electron Microscopy inspection.
|By cleaving the sample it is possible to inspect ALD coatings deposited on Si trenches in cross-sectional mode.
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:03_ALD_eves_AZO.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.800000000000000000000000000000
|Ion Beam Etching (IBE).
|Opening of deposited AZO top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching.
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:04_ALD_eves.jpg|250x350px|center]]
|-
|-
!1.900000000000000000000000000000
|Scanning Electron Microscopy inspection.
|By cleaving the sample it is possible to inspect IBE etching results in cross-sectional mode.
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:05_ALD_eves_ICP.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.10000000000000000000000000000000
|Selective etch of Si between ALD AZO coatings.
|Si etching proceeds using reactive ion etching with isotropic process based on SF<sub>6</sub> process gas.
||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]].
|[[image:06_ALD_eves.jpg|250x350px|center]]
|-
|-
!1.110000000000000000000000000
|Scanning Electron Microscopy inspection of fabricated structure.
|Proof of final result.
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:07_ALD_eves_RIE_SF6.jpg|250x350px|center]]
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|}
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