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LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions

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Created page with "====Procces flow description==== The substrates for the samples were fabricated by depositing 1 μm of Si<sub>3</sub>N<sub>4</sub> (the resonator layer) on 100 mm silicon < 1..."
 
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image:TiO2nanorings.jpg| High aspect ratio Al<sub>2</sub>O<sub>3</sub> and TiO<sub>2</sub> nanogratings.
image:TiO2nanorings.jpg| High aspect ratio Al<sub>2</sub>O<sub>3</sub> and TiO<sub>2</sub> nanogratings.
</gallery>
</gallery>
== Process flow ==
Hej Evgeniy <br>
Jeg har lagt dette eksemple på et process flow ind. Alt tekst og billeder skal selvfølgelig erstattes af relevante process steps for denne artikel.
Mvh. Berit
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-
|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-
|-
!1.1
|Plasma surface treatment
|To ensure clean surface, the 100 mm Si wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]]
|[[image:00_zero (1)_nanogratings.JPG|250x350px|center|]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.2
|DUV Resist patterning
|DUV
|[[Specific_Process_Knowledge/Lithography/DUVStepperLithography|DUV Stepper Lithography]].
|[[image:00_zero (2)_nanogratings.JPG|250x350px|center|]]
|-
|-
!1.3
|Deep reactive ion etching (DRIE)
|DRIE; [[Specific_Process_Knowledge/Etch/DRIE-Pegasus/DUVetch|Recipe: PolySOI10]]
| [[Specific_Process_Knowledge/Etch/DRIE-Pegasus|DRIE Pegasus]].
|[[image:00_zero (3)_nanogratings.JPG|250x350px|center|]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.4
|Plasma surface treatment
|To ensure that remainings of DUV resist are gone, samples are treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step)
|[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]].
|
|-
|-
!1.5
|Scanning Electron Microscopy inspection
|By cleaving the sample it is possible to inspect DRIE etched Si trenches in cross-sectional mode
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:Si_trenches_nanogratings.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.6
|Atomic Layer Deposition of either Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub>
|Deposition carried at 150C.Thickness is 90 nm.
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipes used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/Al2O3_deposition_using_ALD#Al2O3_recipe_for_deposition_on_high_aspect_ratio_structures| Al2O3T]] and [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] .
|[[image:00_zero (4)_nanogratings.JPG|250x350px|center]]
|-
|-
!1.7
|Scanning Electron Microscopy inspection
|By cleaving the sample it is possible to inspect ALD coatings deposited on Si trenches in cross-sectional mode
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_coating_nanogratings.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.8
|Opening of deposited Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> top layers.
|Etching happens using ICP Metal etcher with Cl<sub>2</sub>/BCl<sub>3</sub> process gasses.
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].
|[[image:00_zero (6)_nanogratings.JPG|250x350px|center]]
|-
|-
!1.9
|Scanning Electron Microscopy inspection
|By cleaving the sample it is possible to inspect ICP etcher results Si trenches in cross-sectional mode
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_top_removal_nanogratings.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.10
|Selective etch of Si between ALD  Al<sub>2</sub>O<sub>3</sub> or TiO<sub>2</sub> coatings.
|Si etching proceeds using ICP Metal etcher with isotropic  process based on SF<sub>f</sub> process gas.
||Equipment used: [[Specific_Process_Knowledge/Etch/ICP_Metal_Etcher|Metal ICP Etcher]].
|[[image:00_zero (7)_nanogratings.JPG|250x350px|center]]
|-
|-
!1.11
|Scanning Electron Microscopy inspection of fabricated structure.
|Proof of final result.
|
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]]
<br clear="all" />
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]]
|[[image:TiO2_grating_nanogratings.jpg|250x350px|center]]
|-
|-
|- style="background:#BCD4E6; color:black"
!1.12
|Ion beam etching. (Optional)
|Additional shape of the top part. 20 mijn etch using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage shoud be placed to 0<sup>o</sup> degree. SEM cross section is used for inspection
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]]
|[[image:image1004_nanogratings.jpg|250x350px|center]]
|-
|-
|}
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