LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/TiO2 Q plates: Difference between revisions
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'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/LabAdviser/Technology_Research/Fabrication_of_Hyperbolic_Metamaterials_using_Atomic_Layer_Deposition/TiO2_Q_plates click here]''' | |||
<i>This page is written by <b>Evgeniy Shkondin @DTU Nanolab</b> if nothing else is stated. <br> | |||
All images and photos on this page belongs to <b>DTU Nanolab</b> and <b>DTU Electro</b> (previous DTU Fotonik).<br> | |||
The fabrication and characterization described below were conducted in <b>2013-2016 by Evgeniy Shkondin, DTU Nanolab</b>.<br></i> | |||
====Procces flow description==== | ====Procces flow description==== | ||
A 500 μm thick wafer of silica (SiO<sub>2</sub>) goes through RCA clean and low-pressure chemical vapor deposition (LPCVD) (furnace from Tempress) based on SiH<sub>4</sub> (silane) at 560<sup>◦</sup>C to form a layer of 300 nm of amorphous silicon (Si) [Fig. 1]. The back side of deposited Si was etched using KOH wet etch. In order to remove residues from the etching process, it was performed oxygen plasma cleaning. A CSAR resist was spin-coated to the thickness of 150 nm, followed by exposure of Electron Beam Lithography (EBL) (JEOL JBX-9500 Electron-beam) generating a mask with concentric ring patterns. After development, the wafer was submitted to advanced silicon etch (ASE). To form the trenches of the TiO<sub>2</sub> structures, a thin film of TiO<sub>2</sub> was deposited using the ALD technique in a hot-wall system (Picosun R200), working with 2000 cycles at 150<sup>◦</sup>C [Fig.1]. The precursors used were titanium tetrachloride (TiCl<sub>4</sub>) and H<sub>2</sub>O (supplied by Strem Chemicals Equipment). The process was followed by Ar<sup>+</sup> ion beam etching (IBE) on both sides of the wafer to remove excess of ALD deposited material. At the top most TiO<sub>2</sub> layer the physical sputtering of the sample using Ar<sup>+</sup> ions was performed in order to get access to Si core. On the backside, the Ar<sup>+</sup> ions were used to remove the deposited TiO<sub>2</sub>. Finally, we performed a reactive ion etch on silicon, leaving only the TiO<sub>2</sub> structures. The final system comprehends a base of SiO<sub>2</sub> with nano-structures of TiO<sub>2</sub> on it. Figure 2 shows the image of the system taken using scanning electron microscope (SEM) and conventional optical microscope. Figure 3 illustrates SEM cross-sectional image of the prepared Q-plate . | |||
<gallery caption="" widths="1000px" heights="600px" perrow="1"> | <gallery caption="" widths="1000px" heights="600px" perrow="1"> | ||
image: | image:Q_plates_fab_sheme_new.jpg| Figure 1. Scheme of fabrication flow. | ||
</gallery> | </gallery> | ||
<gallery caption="" widths="1000px" heights="600px" perrow=" | <gallery caption="" widths="1000px" heights="600px" perrow="2"> | ||
image:TiO2nanorings.jpg| | image:TiO2nanorings.jpg| Figure 2. TiO<sub>2</sub> concentric nanorings acting as a Q-plate. Insets show optical and SEM images of the whole plate. | ||
image:Q_plates_cross_section.jpg| Figure 3. Cross-sectional SEM image of the TiO<sub>2</sub> Q-plate. a) The low magnification image shows the whole plate b) High magnification allows to inspect individual rings cross-sections. | |||
</gallery> | </gallery> | ||
== Process flow == | |||
Description of steps for fabrication of Q-plates. | |||
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;" | |||
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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step | |||
!width="250px" style="background:#6495ED; color:black"|Description | |||
!width="200px" style="background:#6495ED; color:black"|LabAdviser link | |||
!width="260px" style="background:#6495ED; color:black"|Image showing the step | |||
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!1.1 | |||
|RCA clean. | |||
|Before Si deposition in LPCVD furnace, the quartz (fused silica) wafers need to be cleaned | |||
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA| RCA]] | |||
|[[image:Zero1.jpg|250x350px|center|]] | |||
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|- style="background:#BCD4E6; color:black" | |||
!1.2 | |||
|Low-Pressure Chemical Vapour Deposition (LPCVD) of Si. | |||
|LPCVD deposition of 300 nm amorphous Si | |||
|[[Specific_Process_Knowledge/Thin_film_deposition/Furnace_LPCVD_PolySilicon| 6" LPCVD polysilicon furnace (E2)]]. | |||
|[[image:Zero2.jpg|250x350px|center|]] | |||
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!1.3 | |||
|Si anisotropic wet etch. | |||
|Removal of the Si from the back side of the wafer. | |||
| [[Specific_Process_Knowledge/Etch/KOH_Etch|KOH]]. | |||
|[[image:Image1_Si_on_SiO2.jpg|250x350px|center|]] | |||
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|- style="background:#BCD4E6; color:black" | |||
!1.4 | |||
|Plasma surface treatment. | |||
|To ensure that all organic remainings are gone, wafer is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | |||
| | |||
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]] | |||
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[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]] | |||
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!1.5 | |||
|E-Beam Lithography (EBL). | |||
|Spin-coating of CSAR resist to the thickness of 150 nm, followed by e-beam exposure. | |||
| | |||
[[Specific_Process_Knowledge/Lithography/EBeamLithography/JEOL_9500_User_Guide|JEOL JBX-9500 Electron-beam]] | |||
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|[[image:Image2_ebeam_on_Si.jpg|250x350px|center]] | |||
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|- style="background:#BCD4E6; color:black" | |||
!1.6 | |||
|Advanced Silicon Etching. | |||
|Creating sacrificial silicon template. | |||
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[[Specific_Process_Knowledge/Etch/ASE_(Advanced_Silicon_Etch)|ASE]] | |||
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|[[image:Image3_ASE_of_SI.jpg|250x350px|center]] | |||
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!1.7 | |||
|Scanning Electron Microscopy inspection. | |||
|The fabricated template inspects by SEM | |||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]] | |||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]] | |||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]] | |||
|[[image:Si_template_q_plates.jpg|250x350px|center]] | |||
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|- | |||
|- style="background:#BCD4E6; color:black" | |||
!1.8 | |||
|Plasma surface treatment. | |||
|To ensure that all organic remainings are gone, template is treated by O<sub>2</sub>/N<sub>2</sub> plasma. (Optional step) | |||
| | |||
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_Asher_2| Plasma Asher 2]] | |||
<br clear="all" /> | |||
[[Specific_Process_Knowledge/Lithography/Strip#Plasma_asher| Plasma Asher 1]] | |||
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!1.9 | |||
|Atomic Layer Deposition (ALD) of TiO<sub>2</sub>. | |||
|Deposition carried at 150C.Thickness is approx. 90 nm. | |||
||Equipment used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200|ALD Picosun R200]]. Standard recipe used: [[Specific_Process_Knowledge/Thin_film_deposition/ALD_Picosun_R200/TiO2_deposition_using_ALD#TiO2_deposition_on_trenches| TiO2T]] . | |||
|[[image:Image4_ALD_of_SI_template.jpg|250x350px|center]] | |||
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|- style="background:#BCD4E6; color:black" | |||
!1.10 | |||
|Ion Beam Etching (IBE). | |||
|Opening of deposited TiO<sub>2</sub> top layer using recipe [[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Ti_etch|"Ti acceptance"]] there the stage was placed to 0<sup>o</sup> degree. The back side of the wafer also needs to be exposed to etching. | |||
|[[Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300|IBE/IBSD Ionfab 300]] | |||
|[[image:Image5_ALD_Ar_sputtering.jpg|250x350px|center]] | |||
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|- | |||
!1.11 | |||
|Scanning Electron Microscopy inspection. | |||
|SEM inspection of ALD deposition and IBE etching. | |||
| | |||
[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]] | |||
<br clear="all" /> | |||
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]] | |||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]] | |||
|[[image:top_removal_q_plates.jpg|250x350px|center]] | |||
|- | |||
|- | |||
|- style="background:#BCD4E6; color:black" | |||
!1.12 | |||
|Selective etch of Si between ALD TiO<sub>2</sub> coatings. (Reactive Ion Etching) | |||
|Si etching proceeds using Reactive Ion Etching (RIE) with isotropic process based on SF<sub>6</sub> process gas. | |||
||Equipment used: [[Specific_Process_Knowledge/Etch/RIE_(Reactive_Ion_Etch)|RIE2]]. | |||
|[[image:Image6_ALD_Final_structure.jpg|250x350px|center]] | |||
|- | |||
|- | |||
!1.13 | |||
|Scanning Electron Microscopy inspection. | |||
|Proof of final result. | |||
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[[Specific_Process_Knowledge/Characterization/SEM_Supra_1|SEM Supra 1]] | |||
<br clear="all" /> | |||
[[Specific_Process_Knowledge/Characterization/SEM_Supra_2|SEM Supra 2]] | |||
<br clear="all" /> | |||
[[Specific_Process_Knowledge/Characterization/SEM_Supra_3|SEM Supra 3]] | |||
|[[image:Si_removal_q_plates.jpg|250x350px|center]] | |||
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|} | |||
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