Aligned exposure on JEOL 9500

There is quite a few things to remember in order to align an exposure to an existing pattern. The example below is a step by step guide illustrating global substrate alignment as well as chip alignment. If your job only requires global alignment simply skip the chip alignment part.

Job preparation

The job illustrated below writes a chip layout in a 5 x 5 matrix into a 2 x 2 matrix as illustrated in the figure. The first layer, L1, has defined global marks at P = (-30000,0) and Q = (30000,0). The local chip marks are placed at M1 = (-450,450), M2 = (450,450), M3 = (450,-450) and M4=(-450,-450).

Chip alignment requires a global alignment to be made first to establish the wafer coordinate system. Hence a global alignment using GLMDET is used initially as in the example above. To further illustrate chip alignment we will look at a particular layout shown below. The layout also illustrates a commonly used feature on the JEOL system to create arrays of arrays. In the layout below there is main 2x2 array and into each of these is a 5x5 subarray. Each element of the subarray is a single chip with four chip alignment marks. Notice that array placement is given in the substrate coordinate system and so is the global mark positions. Chip alignment marks (M1-M4) are however given in the local chip coordinate system. In the example files below we assume L1 is already defined on the substrate and we wish to align L2 to it.

Since a pattern (V30 file) is placed at the center of the bounding box it is essential to control the bounding box of the chip design. The design in this case appears symmetric around (0,0) but in order to force it to be symmetric it is common to place corner marks at equidistance points from (0,0). The corner marks can be 1 nm boxes that will not show up in the resist when developed.

Illustration of chip alignment using a chip array instanced into another array. Notice in the right most illustration how four corner marks are used to force symmetry around (0,0) such that the pattern is placed correctly.

Chip alignment SDF

MAGAZIN	'THOPE'

#8
%4C     
JDF	'thope230126',1
ACC 100
CALPRM '6na_ap5'
DEFMODE 2      
GLMDET S	
CHIPAL 1
HSWITCH OFF,ON
RESIST 250
SHOT A,6
OFFSET(-44,-139)

END 8

CHIPAL [mode]

CHIPAL has six modes

0 - Cancels chip alignment
S - SEM mode. The user is prompted to use SEM mode to manually find M1
1 - One mark is used for position correction
4 - Four marks are used for position, rotation and gain correction
V1 - Virtual mode 1. A single mark position is used for height detection of the substrate, no position correction
V4 - Virtual mode 4. Four mark positions are used for height detection of the substrate, no position correction

In addition to position correction mode 1 and 4 also detects substrate height. The virtual modes are only used to detect substrate height since no mark detection is done. Mode S obviously very time consuming for a high number of chips.

If set up properly on good quality marks mode 1 or mode 4 chip alignment can usually execute in about 1-2 seconds per mark. The time estimate at compilation will account for the time spend on chip alignment at the current settings of the CHIPAL subprogram.

Chip alignment JDF

In addition to the use of CHMPOS for chip mark position definition the example below illustrate making arrays of an array. The first array is set up as a 2x2 array assigning array A1. A1 is defined below as 1:, since 1 is defined as an array it can be referenced as A1. A then defines a 5x5 array assigning pattern P(1) to each element. The chip mark position command must be used in the same array that assigns the corresponding pattern.

JOB/W    'THOPE',4  ; 4inch wafer

GLMPOS    P=(-30000,0),Q=(30000,0)

PATH FT01
  ARRAY	(-15000,2,30000)/(10000,2,20000)
	ASSIGN A(1) -> ((1,1))	

1: 	ARRAY (-4000,5,2000)/(4000,5,2000)
	CHMPOS M1=(-450,450),M2=(450,450),M3=(450,-450),M4=(-450,-450)
	ASSIGN P(1) -> (*,*)

  AEND
PEND

LAYER	1	
        P(1)  'thope230126.v30'
        SPPRM 4.0,,,,1.0,1
        STDCUR  6

END

CHMPOS [M1=(x1,y1){,M2=(x2,y2),M3=(x3,y3),M4=(x4,y4)}]

CHMPOS defines the chip alignment marks in the local chip coordinate system, unit is µm. M1 is mandatory while M2-M4 are optional in one mark mode. In four mark mode all marks must be defined. The order of the marks is important, M1 must be top left with M2-M4 placed clockwise around the center. In the given example the four marks are placed symmetrically at ±450 µm in x and ±450 µm in y.

It V1 mode it is customary to set M1 = (0,0) such that substrate height is detected at the center of the chip. In this way V1 mode can be used to exactly read out substrate height where the chip pattern will be written.