Specific Process Knowledge/Etch/DryEtchProcessing

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Techniques, hardware and challenges common to all dry etch tools

This page contains information that is common to dry etch instruments.

Hardware and option comparison of the dry etchers at Danchip

The table below compares the hardware and the options.

		RIE2	ASE	AOE	DRIE-Pegasus	ICP Metal etch	III-V RIE	III-V ICP
Purpose	Primary uses	The RIE chamber for etching of: silicon silicon oxides/nitrides The users are allowed to have 5% metal exposed to the plasma	Formerly the primary silicon etcher; now polymers may also be etched	Etching of silicon oxides or nitrides	Silicon etching	Standard recipes for etching of Al, Cr and Ti, now also etches of W, TiW and Mo	Etching of silicon oxide, resist, BCB, silicon nitride, InP, InGaAs and GaAs on III-V substrates	Etching of III-V materials such as GaN, InP/InGaAsP/InGaAs, AlGaAs, GaAs
	Alternative/backup uses	Shallow silicon etches	Backup silicon etcher		Barc etch	Silicon etcher
General description	Plasma source	Parallel plate capacitor setup with RF power between the two electrodes	Inductively coupled plasma chamber with two RF generators; the coil and platen generator	Inductively coupled plasma chamber with two RF generators; the coil and platen generator	Inductively coupled plasma chamber with two RF generators; the coil (with outer and inner coil) and platen generator	Inductively coupled plasma chamber with two RF generators; the coil and platen generator	Parallel plate capacitor setup with RF power between the two electrodes	Inductively coupled plasma chamber with two RF generators; the coil and platen generator
	Substrate cooling/temperature	The electrode is oil cooled: Fixed at 20oC	The electrode is oil cooled. Also, Helium backside cooling: -10oC to 20oC	The electrode is oil cooled. Also, Helium backside cooling: -10oC to 60oC	The electrode is oil cooled. Also, Helium backside cooling: 0oC to 50oC	The electrode is oil cooled. Also, Helium backside cooling: -20oC to 30oC	The electrode is oil cooled: Fixed at 20oC	The electrode is oil cooled with a special chiller. Also, Helium backside cooling: 20oC to 180oC
	Clamping	No clamping	Electrostatic clamping (semco electrode)	Electrostatic clamping (TDESC)	Electrostatic clamping (TDESC)	Electrostatic clamping (TDESC)	No clamping	Mechanical clamping (weighted clamp with ceramic fingers)
	Gasses	SF6 O2 CF4 N2 Ar CHF3	SF6 O2 C4F8 Ar CO2	SF6 O2 C4F8 H2 CF4 He	SF6 O2 C4F8 Ar	SF6 O2 C4F8 Ar CF4 H2 CH4 BCl3 Cl2 HBr	O2 CHF3 CH4 Ar H2	SF6 O2 CF4 Ar CH4 H2 HBr BCl3 Cl2
	RF generators	RF generator	Coil generator Platen generator	Coil generator Platen generator	Coil generator Platen generator Low frequency platen generator	Coil generator Platen generator	RF generator	Coil generator Platen generator
	Substrate loading	Loading via cluster 2 load lock	Loading via dedicated two-slot carousel load lock	Loading via dedicated two-slot carousel load lock	Loading via dedicated two-slot carousel load lock or via atmospheric cassette loader	Loading via dedicated two-slot carousel load lock	Manual loading directly into process chamber	Loading via dedicated two-slot carousel load lock
	Options	Optical endpoint detector at fixed wavelength	Bosch multiplexing Parameter ramping		Bosch multiplexing Parameter ramping SOI option Optical endpoint detection	Parameter ramping Optical endpoint detection	Laser endpoint detection	Parameter ramping Bosch multiplexing Optical endpoint detection Laser endpoint detection
Allowed materials		Silicon Fused silica Sapphire SiC	Silicon Fused silica Sapphire SiC	Silicon Fused silica Sapphire SiC	Silicon Fused silica Sapphire SiC	Silicon Fused silica Sapphire SiC	Silicon Fused silica Sapphire SiC GaAs, GaN, InP, with epitaxial layers	Silicon Fused silica Sapphire SiC GaAs, GaN, InP, with epitaxial layers

Temporary bonding of wafers or chips for dry etching

Purpose

Many tools are set up for processing one particular size of wafer. The reasons why a tool processes one size of wafers and not others are numerous - they may include:

• Hardware availability
• Processes required by users

The dry etch tools at Danchip all have a default wafer size and may have other sizes of electrodes available. Other sizes of wafers or chips may also be processed but they will requrie the use of a carrier wafer. Using a carrier is also often required if the side of the wafer facing the electrode has structures.

Processesing different sizes of wafers or chips in the dry etch tools at Danchip

Tool	Default substrate size	Alternative substrate size(s)	Sizes of wafers or chips that may bonded and processed
DRIE-Pegasus	4" wafer	6" wafer	Samples smaller than a 4" wafer
RIE	4" wafer	None	Samples smaller than a 4" wafer
ASE	4" wafer	6" wafer	Samples smaller than a 4" wafer
AOE	4" wafer	None	Samples smaller than a 4" wafer
ICP Metal Etch	6" wafer	4" wafer	Samples smaller than a 6" wafer
III-V ICP	4" wafer	None	Samples smaller than a 4" wafer

Issues to consider

There are several issues to consider when processing a substrate that is lying (either fixed with a bonding material or lying freely) on a carrier.

Process temperature

The cooling of a wafer that is lying directly on the electrode is significantly more efficient than if the wafer is lying on top of a carrier. With no bonding material the wafer is essentially only touching the carrier in three points - thus drastically reducing the heat transfer to the electrode. The possible change in substrate temperature may cause the process to drift or the mask to burn away much faster. Using a bonding material such as crystal bond will increase the heat transfer between carrier and substrate.

Process aggressiveness and material removal

The chemical etching of materials (for instance if silicon is etched by flourine) releases energy that has to dissipated to the electrode. This release of energy depends on two factors:

1. The faster the etch rate is, the more material is removed pr second, hence the more heat needs to be dissipated. This means that high power etches are much more sensible to poor heat transfer than low power processes.
2. The larger area of the wafer that is etched, the more material is removed pr second. Hence, wafers with a high density of areas open for etching, will be more sensible to poor heat conductivity than wafers with little opening.

Plasma uniformity

The plasma will adapt to the substrate+carrier sandwich and bow along the edges of the substrate potentially disturbing the electric field that directs the ions towards the surface. This non-uniformity can be important if the substrate is very small.

Procedures

Bonding

1. Find a carrier wafer that has the right size. Keep in mind that it matters a great deal if the surface will be etched or not, i.e. if it has oxide or not.
2. Take a piece of crystalbond from the shelf in cleanroom 1.
3. Take your items (substrate, carrier wafer, crystalbond and tweezers) to the hotplate in cleanroom 1.

4. Put the carrier wafer on the hotplate. A 6" wafer will fit not in the recess but it will get sufficiently hot if you leave it there for some seconds longer.
5. Apply a very thin layer of crystalbond in a circular motion so that it covers some 70 % of the area to be covered by your substrate. Do not apply too much! Little does it..
6. Gently put your wafer on the crystalbond.
7. Using two pairs of tweezers gently massage your substrate in a circular motion in order to distribute the crystalbond evenly between the substrate and carrier while making sure that it doesn’t get exposed on the carrier.
8. If you are bonding two wafers of the same size (for instance in etch-through applications) make sure that the flats and wafer peripheries are perfectly aligned.
9. Once the substrate is in the right place, cool the bonded sandwich, for instance by placing it on an aluminium block from the spinner.
10. Make sure that there’s no trace of crystalbond on the backside of the carrier wafer (the side of the wafer that will face the TDESC) and you’re ready.

Keep in mind always to use the same kind of carrier wafer. The process conditions change dramatically if you use a blank silicon wafer instead of a wafer with a few hundred nanometers of thermal oxide when processing a, say, 2" wafer - the area of silicon exposed to plasma is quite different.

Debonding

Separating a bonded set of wafers or chips may sometimes be tricky and there is no straight forward procedure for all applications. The crystalbond dissolves in water and it melts around 65°C, so one can try one of the following procedures (that increase in aggressiveness).

• Placing the bonded sandwich on the hotplate will release the substrate. Dry with wet cleanroom cloth.
• Wash with DI water
• Wash with DI water, acetone and IPA (any photo resist on your wafer?)
• Wash with DI water, acetone and IPA and use the plasma asher