Specific Process Knowledge/Thermal Process/Annealing

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Revision as of 13:08, 25 January 2008 by BGE (talk | contribs) (New page: ==Annealing== At Danchip we have ? furnaces for oxidation: A1,A3,C1,C2,C3 and D1. Annealing can take place either by a dry process or a wet process. In a wet annealing you will also get so...)
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Annealing

At Danchip we have ? furnaces for oxidation: A1,A3,C1,C2,C3 and D1. Annealing can take place either by a dry process or a wet process. In a wet annealing you will also get some oxidation.

  • Dry anneal is used from 5nm - 200nm. Can be grown in furnaces:A1,A3,C1,C2,C3.
  • Wet anneal with H2O in a bubbler can be grown in furnaces:C1,C2,C3.

Comparing the six oxidation furnaces

' A1 Boron drive-in A3 Phosphorous drive-in C1 Gate oxide C2 Anneal oxide C3 Anneal bond D1 APOX
General description Drive-in of boron deposited in the boron pre-dep furnace(A2) or drive-in of ion implanted boron. Can also be used for dry and wet oxidation. Drive-in of phosphorous deposited in the phosphorous pre-dep furnace(A2) or drive-in of ion implanted phosphorous. Can also be used for dry and wet oxidation. Oxidation of gate-oxide and other especially clean oxides. At the moment also used for general oxidation of 6" wafers. Oxidation and annealing of wafers from the B-stack and PECVD1. Oxidation and annealing of wafers from NIL. Oxidation of very thick oxides
Dry oxidation x x x (with special permission) x x
wet oxidation with torch (H2+O2) x x
Wet oxidation with bubler (water steam + N2) x (with special permission) x x x
Process temperature 800-1150 oC 800-1150 oC 800-1150 oC 800-1150 oC 800-1150 oC 1150 oC
Cleanliness of dry oxide (rated 1-4, 1 is best) 2 2 1 3 4
Cleanliness of wet oxide (rated 1-4, 1 is best) 1 1 2 3 4 3
Batch size max. 30 wafers of 4" or 2" max. 30 4" wafers or 2" wafers max. 30 wafers of 6",4" or 2" max. 30 4" wafers or 2" wafers max. 30 4" wafers or 2" wafers max. 200 4"
Which wafers are allowed to enter the furnace: A1 Boron drive-in A3 Phosphorous drive-in C1 Gate oxide C2 Anneal oxide C3 Anneal bond D1 APOX
New clean* Si wafers 4" (6" in C1) x x x (with special permission) x x x
RCA clean** Si wafers with no history of Metals on x x x (with special permission) x x
From Predep furnace directly (e.g. incl. Predep HF**) From A2 From A4
Wafers directly from PECVD1 x x
Wafers directly from NIL bonding x

*New clean: only right from the new clean box. It is not allowed to put them in another box first.

**These wafers must be placed in a "transport box from RCA to furnace" using the RCA carrier when doing RCA or the pre-dep carrier after pre-dep.