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Slow etch of SiO2 with resist as masking material - using a 6" carrier wafer with recess
This recipe can be used for slow etching of SiO2 with resist as masking material. Here are some test results presented.
| Parameter
|
Resist mask
|
| Coil Power [W]
|
200
|
| Platen Power [W]
|
25
|
| Platen temperature [oC]
|
0
|
| CF4 flow [sccm]
|
20
|
| H2 flow [sccm]
|
10
|
| Pressure [mTorr]
|
3
|
| Results
|
Test on wafer with 50% load (Travka 50), by BGHE @danchip
|
| Etch rate of thermal oxide
|
44.1 nm/min (50% etch load) (01-02-2014)
|
| Selectivity to resist [:1]
|
~0.9
|
| Wafer uniformity (100mm)
|
±1.6% (01-02-2014)
|
| Profile [o]
|
Take a look at the images but be aware that the resist profile was not good to begin with.
|
| Wafer uniformity map (click on the image to view a larger image)
|
Contour plot of the etch rate over the wafer, 9 points measured
|
| SEM profile images
|
-
Resist profile before etch
-
Resist profiler after etch 01-02-2014.
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Resist profiler after etch 01-02-2014. No line width reduction observed.
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