Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE

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The Bosch process: Etching of silicon

The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.

In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.

Quality control procedure on the ASE

Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.

  • Shallolr: The shallow etch process will etch a 2 µm opening down to make a 20 µm trench.
  • Deepetch: The deep etch process will etch a 50 µm opening down to make a 300 µm trench.

The standardization procedure on the ASE covers these two etches.

Quality Control (QC) for ASE
QC Recipe: Shallolr (2 µm trench)
Common parameters Multiplexed parameters
Parameter Setting Parameter Etch Passivation
Temperature 10oC SF6 Flow 260 sccm 0 sccm
No. of cycles 31 O2 Flow 26 sccm 0 sccm
Process time 5:56 mins C4F8 Flow 0 sccm 120 sccm
APC mode manual RF coil 2800 W 1000 W
APC setting 86.8 % RF Platen 16 W 0 W
Cycle time 6.5 s 5 s
QC limits ASE
Etch rate in Si 3 - 4 µm/min
Non-uniformity 5 %


QC Recipe: Deepetch (50 µm trench)
Common parameters Multiplexed parameters
Parameter Setting Parameter Etch Passivation
Temperature 20oC SF6 Flow 230 sccm 0 sccm
No. of cycles 250 O2 Flow 23 sccm 0 sccm
Process time 54:10 mins C4F8 Flow 0 sccm 120 sccm
APC mode manual RF coil 2800 W 1000 W
APC setting 87.7 % RF Platen 19 W 0 W
Cycle time 8 s 5 s
QC limits ASE
Etch rate in Si 4 - 6 µm/min
Non-uniformity 5 %

Recipes on the ASE

Shallolr

The shallolr recipe is designed to etch features (with sizes above 1 µm) in silicon down to a depth that ranges from a few microns to some 50 microns. (If you need to etch deeper use Deepetch or more shallow, see Nanoetches.) It is specified to etch a 2 µm wide trench down to a depth of 20 µm on a wafer that has a global/local etch opening density of 10%.

The recipe is given above.

The process runs for 31 cycles (5:56 mins). The fact that it's Bosch process is clear from the scallops on the sidewalls - one should be able to count 31 of them.

The process is designed to reach 20 µm down in a 2 µm trench but as is clear from the image of the corresponding 50 µm trench, this one is etched deeper. The reason is the so called Aspect Ratio Dependent Etching or ARDE: See below.

Deepetch

The deepetch recipe is designed to etch features (with sizes 2 µm) in silicon down to a depth that ranges from some 50 microns to hundreds of microns. (If you need to etch less, use shallow or Nanoetches.) It is specified to etch a 50 µm wide trench down to a depth of 300 µm on a wafer that has a global/local etch density of 10%.

As is clear from the two images ARDE also plays a role in this case: The 2 µm trench (widened to about 5-6 µm because of undercut/underetching) is only etched 150 µm.

Iso

The recipe Iso is the same recipe as Deepetch but without the passivation steps.
It has been tested once by Filip Sandborg-Olsen @nanotech.
He etched with 100% load for 10 min. He got an etch rate of 5.51µm/min

Process development

Etch of nano sized structures

Older work: Three different examples of etch are shown here. The masking material was zep520A (80 nm). By BGHE@dtu.dk

Vertical sidewalls Low ARDE Positive tappered side walls

Etch cycle

  • SF6 flow [sccm]:50
  • C4F8 flow [sccm]:100
  • Pressure [mTorr] 20
  • Coil power [W]: 350
  • Platen power [W]: 30
  • Cycle Time [s]: 5

Dep. Cycle

  • C4F8 flow [sccm]: 100
  • Pressure [mTorr]: 20
  • Coil power [W]: 500
  • Platen power [W]: 0
  • Cycle Time [s]: 3
  • Temperature [Deg. C] 20

Results:

  • Etch rate of 100nm lines: 146nm/min @etch time: 1:36min.

Etch cycle

  • SF6 flow [sccm]:50
  • C4F8 flow [sccm]:100
  • Pressure [mTorr] 10
  • Coil power [W]: 350
  • Platen power [W]: 30
  • Cycle Time [s]: 5

Dep. Cycle

  • C4F8 flow [sccm]: 100
  • Pressure [mTorr]: 10
  • Coil power [W]: 500
  • Platen power [W]: 0
  • Cycle Time [s]: 3
  • Temperature [Deg. C] -10

Results:

  • Etch rate of 100nm lines: 131nm/min @etch time: 1:36min.

Etch cycle

  • SF6 flow [sccm]:50
  • C4F8 flow [sccm]:100
  • Pressure [mTorr] 10
  • Coil power [W]: 350
  • Platen power [W]: 10
  • Cycle Time [s]: 5

Dep. Cycle

  • C4F8 flow [sccm]: 100
  • Pressure [mTorr]: 10
  • Coil power [W]: 500
  • Platen power [W]: 0
  • Cycle Time [s]: 3
  • Temperature [Deg. C] 20

Results:

  • Etch rate of 100nm lines: 209nm/min @etch time: 2:56min.

Etching Si without back side cooling

Etching in an ICP as the ASE without backside cooling normally results in heating up the sample to more than 100 degrees Celsius. This can be problematic especially when using resist as a masking material.

There can be many reasons for not applying cooling to the sample. Among these are samples that need to be processed on a carrier due to sensitive backsides, sticky backsides or structures on the backside, small samples, membranes that can break, bowing wafers or something else.

To meet these needs we have developed a silicon etch in the RIE mode where the coil power is not being used. The coil creates a high density plasma and that has a higher plasma temperature than a low density plasma created by the platen power in RIE mode.

This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power.

Recipe name in the ASE: "1si_rie1"

Wafer ID Resist before etch Platen power Pressure Flow rate SF6 Flow rate O2 Flow rate Ar T Process time Comment Results CD change Profile angles Etch rate in Si Etch rate in resist Selectivity (resist:Si) Etch rate in SiO2
ASE RIE9 3750nm 100W 80mTorr 40sccm 27sccm 0 20 30min HBC off, resist not burned. Microscope images!

.

.

443.3 nm/min

91.7 nm/min

1:4.8

32 nm/min SRN:60 nm/min


ASE RIE8 3750nm 100W 80mTorr 40sccm 27sccm 0 20 4min HBC off Microscope images!

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440 nm/min

nm/min

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