Specific Process Knowledge/Etch/KOH Etch

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KOH etch - Anisotropic silicon etch

KOH belongs to the family of anisotropic Si-etchants based on aqueous alkaline solutions. The anisotropy stems from the different etch rates in different crystal directions. The {111}-planes are almost inert whereas the etch rates of e.g. {100}- and {110}-planes are several orders of magnitude faster.

KOH-etching is a highly versatile and cheap way to realize micro mechanical structures if you can live with the necessary Si₃N₄- or SiO₂-masking materials and the potassium contamination of the surface. The latter necessitates in most cases a wet post-clean ('7-up' or RCA-clean) if the wafer is to be processed further.

At Danchip we use as a standard a 28 wt% KOH. The etch rate - and the selectivity towards a SiO₂-mask - is depending on the temperature. We normally use T=80 ^oC but may choose to reduce this to e.g. 60 ^oC or 70 ^oC in case of a high-precision timed etch (e.g. defining a thin membrane). In some cases we recommend to saturate the standard 28 wt% KOH with IPA with an etch temperature at T=70 ^oC (reduce evaporation of IPA). One example is for boron etch-stop, where the selectivity towards the boron-doped silicon is improved compared to the standard etch.

• Different places to do wet silicon oxide etch
• 
  KOH etch for 4" and 6" wafers. Positioned in cleanroom 4.
• 
  KOH etch for 4" wafers. KOH1 to the left and KOH2 to the right, in between you find the BHF tank. Positioned in cleanroom 3.
• 
  PP-bath: positioned in the upper right corner of the fumehood in cleanroom 2.

Key facts for the different etch baths available at Danchip are resumed in the table:

KOH etching baths

Equipment		KOH3	KOH2	KOH1	KOH Fumehood
Purpose	Wet etch of Silicon	Etch of Silicon in 28 wt% KOH	Etch of Silicon in 28 wt% KOH	Etch of Silicon in 28 wt% KOH saturated with IPA	Etch of Silicon in user mixed KOH
	Link to safety APV and KBA	see APV here see KBA here	see APV here see KBA here	see APV here see KBA here	see APV here see KBA here
Performance	Etch rates in crystalline silicon (100)	0.4 µm/min (60 °C) 0.7 µm/min (70 °C) 1.3 µm/min (80 °C)	0.4 µm/min (60 °C) 0.7 µm/min (70 °C) 1.3 µm/min (80 °C)	0.7 µm/min (70 °C) 0.2 µm/min (70 °C) for Boron doped Si (doping level > 5x1019 cm-3)	Somewhat lower than in the dedicated baths. Approximately 1 µm/min @ 80 °C in 28 wt%
	Etch rates in Thermal SiO2	Theoretical values: 1.2 nm/min (60 °C) 6 nm/min (80 °C)	Theoretical values: 1.2 nm/min (60 °C) 6 nm/min (80 °C)
	Roughness	Typical: 100-600 Å	Typical: 100-600 Å	May form hillocks (pyramidal)	Typical worse than KOH2 and KOH3
	Anisotropy	The etch rate is very dependent on the crystal orientation of the silicon.	The etch rate is very dependent on the crystal orientation of the silicon.	With IPA some crystal planes etches at a slower rate than for KOH without IPA.	The etch rate is very dependent on the crystal orientation of the silicon.
Process parameter range	Chemical solution	28 wt% mixed in the ratio KOH:H2O - 500 g : 1000 ml	28 wt% mixed in the ratio KOH:H2O - 500 g : 1000 ml	28 wt% mixed in the ratio KOH:H2O:IPA - 500 g : 1000 ml : ?? ml	Custom made
	Temperature	Max 80 °C (standard etch)	Max 80 °C (standard etch)	Max 70 °C if IPA added	Max 80 °C
Substrates	Batch size	1-25 wafers at a time	1-25 wafers at a time	1-25 wafers at a time	1-7 wafers at a time
	Size of substrate	4” wafers 6” wafers	4” wafers	4” wafers	2” wafers 4” wafers Small pieces
	Allowed materials	Silicon Silicon oxide Silicon (oxy)nitride	Silicon Silicon oxide Silicon (oxy)nitride	Silicon Silicon oxide Silicon (oxy)nitride	All except for Polymers
	Masking material	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2	Stoichiometric Si3N4 Silicon rich nitride SiN PECVD Si3N4 Thermal SiO2

Definition of structures

Due to the almost inert (111)-planes it is possible by KOH etching to realize high aspect ratio structures in sigle crytalline silicon using the (111)-planes as sidewalls. In Si(100) these sidewalls are inclined - 54.7^o with respect to the (100) surface - whereas in Si(110) the sidewalls are vertical (see figures below).

Si(100)

Si(110)

For Si(100), the relation between the width of the bottom of the etched groove (W_b) and the width of the opening (W_o) at the wafer surface in a groove etched to the depth l is given by:

$W_{b}=W_{o}-2lcot(54.7^{o})=W_{o}-{\sqrt {2}}l$

Definition of <110> alignment structures

The etch rate dependence on the crystallographic planes can be used to determine the <110> crystal directions with high precision (better than +/- 0.05 ^o). A fast method for doing this, using the symmetric under-etching behavior around but not at the <110>-directions, was described by Vangbo and Bäcklund in J. Micromech. Microeng.6 (1996), 279-284. High-precision control of the <110>-direction during alignment can be necessary in order to control the dimensions of KOH-etched structures (e.g. precise control of V-groove dimensions). A dedicated mask (MASK NAME) has been designed for this purpose.

Etch rates: Empirical formula (Seidl et al)

The following empirical formula can be used for concentrations in the range of 10-60 wt%:

R = k₀ [H₂O]⁴ [KOH]^0.25 e^-E_a/kT,

where k₀ = 2480 µm/hr (mol/l)^-4.25, E_a = 0.595 eV for Si(100)

and k₀ = 4500 µm/hr (mol/l)^-4.25, E_a = 0.60 eV for Si(110)