Specific Process Knowledge/Etch/DRIE-Pegasus/processC: Difference between revisions

Revision as of 15:02, 13 December 2012

Process C

Process C is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.

The 100 mm wafers had an Al mask made by lift-off:

80 nm of spin coated ZEP520A E-beam resist
Patterned by E-beam lithograph
20 nm Al deposited and patterned by lift-off
~ 99 % etch load

**Process C specifications**
Parameter	Specification	Average result
Etch rate (µm/min)	Not specified
Etched depth (µm)	300
Scallop size (nm)	< 30
Profile (degs)	85 +/- 5
Selectivity to resist	Not speicified
Undercut (nm)	< 30
Uniformity (%)	< 3.5
Repeatability (%)	<4

**Process C recipe**
Parameter	Etch
Gas flow (sccm)	SF₆ 38 C₄F₈ 70
Process time (mm:ss)	01:30
Pressure (mtorr)	4
Coil power (W)	450
Platen power (W)	100
Common	Temperature 10 degs, HBC 10 torr, long funnel, with baffle & 100 mm spacers

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 == Process C ==
-Process A is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.
+Process C is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.
 The 100 mm wafers had an Al mask made by lift-off: