Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

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==C3 Furnace Anneal Bond==
==C3 Anneal-bond furnace==
[[Image:C3.JPG|thumb|300x300px|C3 Furnace Anneal Bond: positioned in cleanroom 2]]
[[Image:C3.JPG|thumb|300x300px|C3 Anneal-Bond furnace. Positioned in cleanroom 2]]


C3 Furnace Anneal Bond is a Tempress horizontal furnace for oxidation and annealing of silicon wafers.
The C3 Anneal-bond furnace is a Tempress horizontal furnace for oxidation and annealing of (bonded) silicon wafers.


This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that comes directly from bonding in EVG NIL (assuming they were very clean when entering EVG NIL). Check the [http://www.labmanager.danchip.dtu.dk/view_binary.php?fileId=1250 cross contamination chart]. If you are in doubt, please send a mail to [mailto:furnace@danchip.dtu.dk furnace@danchip.dtu.dk].
This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that come directly from bonding in the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the [http://www.labmanager.danchip.dtu.dk/view_binary.php?fileId=1250 cross contamination chart].


'''The user manual, technical information and contact information can be found in LabManager:'''


'''The user manual(s), technical information and contact information can be found in LabManager:'''
'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Furnace C3: Anneal-bond]'''
 
'''[http://www.labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=89 Anneal Bond]'''


==Process knowledge==
==Process knowledge==

Revision as of 13:11, 30 November 2012

C3 Anneal-bond furnace

C3 Anneal-Bond furnace. Positioned in cleanroom 2

The C3 Anneal-bond furnace is a Tempress horizontal furnace for oxidation and annealing of (bonded) silicon wafers.

This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that come directly from bonding in the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the cross contamination chart.

The user manual, technical information and contact information can be found in LabManager:

Furnace C3: Anneal-bond

Process knowledge

Overview of the performance of Anneal Bond furnace and some process related parameters

Purpose Oxidation and annealing Oxidation:
  • Dry
  • Wet: with bubbler (water steam + N2)
Performance Film thickness
  • Dry SiO2: 50 Å to ~2000 Å (takes too long to make it thicker)
  • Wet SiO2: 50 Å to ~5 µm (takes too long to make it thicker)
Process parameter range Process Temperature
  • 800-1150 oC
Process pressure
  • 1 atm
Gas flows
  • N2:5 sccm
  • O2:5 sccm
Substrates Batch size
  • 1-30 4" wafer (or 2" wafers) per run
Substrate material allowed
  • Silicon wafers (new from the box or RCA cleaned)
  • Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
  • Quartz wafers (RCA cleaned)
  • From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)