Specific Process Knowledge/Etch/DRIE-Pegasus

The DRIE Pegasus at Danchip

The SPTS Pegasus in the Danchip cleanroom

The Bosch process

The DRIE Pegasus is a state-of-art silicon dry etcher that offers outstanding performance in terms of etch rate, uniformity etc. It uses the so-called Bosch process to achieve excellent control of the etched features. Click here for more fundamental information of the system.

User manuals etc.

The user manual, quality control procedure and the results may all be found on the DRIE-Pegasus LabManager page.

Important information

In August 2011 we introduced a new set of rules regarding the loading of wafers. In you were trained prior to this, you can find more information here.

Acceptance test

The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found here.

Process information

Process notation

Describing a process recipe on the Pegasus may sometimes be difficult because of the great flexibility of the instrument. A compact and precise notation is therefore required for the recipes. Click here to find a short description of the official SPTS notation.

Standard recipes

• Process A (Large trench): 80 µm wide trench etched down to a depth of 150 µm

• Process B (Via etch): 30 µm diameter via etched down to a depth of 100 µm

• Process C (Nano etch): 50-300 nm posts

• Process D (Micro stamp):

• SOI etch

Other etch processes

• Nanoetch

• Etches that produce positively sloped sidewalls for imprinting purposes

• Maskless reduction of wafer thicknesses

• Very deep etching

Equipment performance and process related parameters

Equipment		Equipment 1
Purpose		Purpose 1 Purpose 2
Performance	Response 1	Performance range 1 Performance range 2
	Response 2	Performance range
Process parameter range	Parameter 1	Range
	Parameter 2	Range
Substrates	Batch size	# small samples # 50 mm wafers # 100 mm wafers # 150 mm wafers
	Allowed materials	Allowed material 1 Allowed material 2

Additional information

Material from SPTS

• Hardware and process applications

• Miscellaneous information