Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

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*Oxidation: look at the [[Specific Process Knowledge/Thermal Process/Oxidation|Oxidation]] page
*Oxidation: look at the [[Specific Process Knowledge/Thermal Process/Oxidation|Oxidation]] page
*Annealing: look at the [[Specific Process Knowledge/Thermal Process/Annealing|Annealing]] page
*Annealing: look at the [[Specific Process Knowledge/Thermal Process/Annealing|Annealing]] page
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==Overview of the performance of Anneal Bond furnace and some process related parameters==
==Overview of the performance of Anneal Bond furnace and some process related parameters==


{| border="2" cellspacing="0" cellpadding="10"  
{| border="2" cellspacing="0" cellpadding="0"  
|-
|-
!style="background:silver; color:black;" align="left"|Purpose  
!style="background:silver; color:black;" align="center"|Purpose  
|style="background:LightGrey; color:black"|Oxidation and annealing
|style="background:LightGrey; color:black"|Oxidation and annealing
|style="background:WhiteSmoke; color:black"|Oxidation:
|style="background:WhiteSmoke; color:black"|Oxidation:
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*Wet: with bubbler (water steam + N<sub>2</sub>)
*Wet: with bubbler (water steam + N<sub>2</sub>)
|-
|-
!style="background:silver; color:black" align="left"|Performance
!style="background:silver; color:black" align="center"|Performance
|style="background:LightGrey; color:black"|Film thickness
|style="background:LightGrey; color:black"|Film thickness
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Dry SiO<sub>2</sub>: 50Å to ~2000Å (takes too long to make it thicker)
*Dry SiO<sub>2</sub>: 50 Å to ~2000 Å (takes too long to make it thicker)
*Wet SiO<sub>2</sub>: 50Å to ~5µm ((takes too long to make it thicker)
*Wet SiO<sub>2</sub>: 50 Å to ~5 µm (takes too long to make it thicker)
|-
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="3"|Process parameter range
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
|style="background:LightGrey; color:black"|Process Temperature
|style="background:LightGrey; color:black"|Process Temperature
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
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|style="background:LightGrey; color:black"|Gas flows
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*N<sub>2</sub>:? sccm
*N<sub>2</sub>:5 sccm
*O<sub>2</sub>:5 sccm
|-
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Substrates
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
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|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Silicon wafers (new from the box or RCA cleaned)
*Silicon wafers (new from the box or RCA cleaned)
**with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
*Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
*Quartz wafers (RCA cleaned)
*Quartz wafers (RCA cleaned)
*From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)
*From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)
|-  
|-  
|}
|}

Revision as of 15:34, 26 November 2012

C3 Furnace Anneal Bond

C2 Furnace Anneal Bond: positioned in cleanroom 2

C3 Furnace Anneal Bond is a Tempress horizontal furnace for oxidation and annealing of silicon wafers.

This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that comes directly from bonding in EVG NIL (assuming they were very clean when entering EVG NIL). Check the cross contamination chart. If you are in doubt, please send a mail to furnace@danchip.dtu.dk.


The user manual(s), technical information and contact information can be found in LabManager:

Anneal Bond

Process knowledge

Overview of the performance of Anneal Bond furnace and some process related parameters

Purpose Oxidation and annealing Oxidation:
  • Dry
  • Wet: with bubbler (water steam + N2)
Performance Film thickness
  • Dry SiO2: 50 Å to ~2000 Å (takes too long to make it thicker)
  • Wet SiO2: 50 Å to ~5 µm (takes too long to make it thicker)
Process parameter range Process Temperature
  • 800-1150 oC
Process pressure
  • 1 atm
Gas flows
  • N2:5 sccm
  • O2:5 sccm
Substrates Batch size
  • 1-30 4" wafer (or 2" wafers) per run
Substrate material allowed
  • Silicon wafers (new from the box or RCA cleaned)
  • Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
  • Quartz wafers (RCA cleaned)
  • From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)
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