Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch): Difference between revisions
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===Limitations using the AOE=== | |||
====Wafer bow==== | |||
There is a limit to how much the wafer can bow and still be clamped on the chuck. The limit can maybe vary a little over time and may also depend on the material on the backside of the substrate. On a 100mm Si wafer with SiO2 on the backside (<10µm) we expect the limit to be around 50µm bow (when the back side surface is convex). | |||
I have been able to etch much deeper in SiO2 with a P-Si mask than with a photo resist mask on a wafer with 50% load. When using photoresist the wafer stopped clamping during the etch after just a few µm. With P-Si can could etch 15µm without problems. I expect this to be due to a combination of P-Si on the back side clamping much better and P-Si on the back side helping to reduce the bow. | |||
====Transparent wafers==== | |||
Transparent wafers are a challange for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test succesfully. | |||
# The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer (could be aluminium). | |||
#The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transfering it into chamber or deposite a more conducting layer on the backside of the wafer. This could be aluminium but also 1-2µm P-Si may be enough. | |||
==A rough overview of the performance of AOE and some process related parameters== | ==A rough overview of the performance of AOE and some process related parameters== | ||