Specific Process Knowledge/Lithography/Aligners/Aligner: Maskless 01 processing: Difference between revisions
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The alignment test with 4 alignment marks shows a +40ppm scaling on the X-axis, as well as a 0.1mRad shearing of the axes. The result is a decent alignment in X, but a shift in Y as well as a relatively large deviation. The raw data shows the deviation in Y is due to a -40ppm scaling along the Y-axis, as seen in the MLA1-MLA1 test with 4 marks, suggesting that the scaling in Y is consistently overestimated. | The alignment test with 4 alignment marks shows a +40ppm scaling on the X-axis, as well as a 0.1mRad shearing of the axes. The result is a decent alignment in X, but a shift in Y as well as a relatively large deviation. The raw data shows the deviation in Y is due to a -40ppm scaling along the Y-axis, as seen in the MLA1-MLA1 test with 4 marks, suggesting that the scaling in Y is consistently overestimated. This is probably also why attempts to use field alignment on structures printed using a different tool always fail at the outer positions. | ||
<br>Aligning using only 2 marks yields acceptable shifts in the center of the wafer, but very large shifts in X towards the edges, as evidenced by the 7.4µm deviation in X. The raw data suggests that this deviation is mainly due to a 0.2mRad tilt in the Y-axis, which corresponds well with the 0.1mRad shearing measured using 4 marks. There is also a (-)40ppm scaling along the X-axis, again similar to what was measured during 4 mark alignment. Even a 5mm chip would be affected by the 0.2mRad tilt, so clearly 4 mark alignment is needed when aligning to a pattern that was not exposed using MLA1. | <br>Aligning using only 2 marks yields acceptable shifts in the center of the wafer, but very large shifts in X towards the edges, as evidenced by the 7.4µm deviation in X. The raw data suggests that this deviation is mainly due to a 0.2mRad tilt in the Y-axis, which corresponds well with the 0.1mRad shearing measured using 4 marks. There is also a (-)40ppm scaling along the X-axis, again similar to what was measured during 4 mark alignment. Even a 5mm chip would be affected by the 0.2mRad tilt, so clearly 4 mark alignment is needed when aligning to a pattern that was not exposed using MLA1. | ||
<br>Attempting to fix the shift in Y when using 4 alignment marks by adding 0;0 as the first mark makes no difference. And the success from the MLA1-MLA1 test when using 3 marks on the bottom half of the wafer is unfortunately not repeated for MLA3-MLA1 alignment. Using alignment marks on the top half of the wafer also doesn't change the shift. The raw data from all the alignment tests using scaling and shearing compensation (3+ marks) shows the best alignment at the bottom of the wafer, with an increasing shift in Y due to a scaling error around -40ppm. Reducing the exposed area reduces the shift in Y, but the raw data show the same trend as the large area; best alignment at the bottom of the exposed area and a scaling error in Y around -40ppm. | <br>Attempting to fix the shift in Y when using 4 alignment marks by adding 0;0 as the first mark makes no difference. And the success from the MLA1-MLA1 test when using 3 marks on the bottom half of the wafer is unfortunately not repeated for MLA3-MLA1 alignment. Using alignment marks on the top half of the wafer also doesn't change the shift. The raw data from all the alignment tests using scaling and shearing compensation (3+ marks) shows the best alignment at the bottom of the wafer, with an increasing shift in Y due to a scaling error around -40ppm. Reducing the exposed area reduces the shift in Y, but the raw data show the same trend as the large area; best alignment at the bottom of the exposed area and a scaling error in Y around -40ppm. | ||