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Specific Process Knowledge/Thermal Process/C2 Furnace III-V oxidation: Difference between revisions

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*Annealing of different samples and sample materials
*Annealing of different samples and sample materials
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!style="background:silver; color:black" align="center"|Performance
!style="background:silver; color:black" align="center" valign="center" rowspan="4"|Process parameter range
|style="background:LightGrey; color:black"|Lateral oxidation rate
|style="background:LightGrey; color:black"|Annnealing temperature
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*Very sample dependent
*Up to 600 <sup>o</sup>C, temperature ramp rate up to 10 <sup>o</sup>C/s
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!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
|style="background:LightGrey; color:black"|Standby temperature
|style="background:LightGrey; color:black"|Process temperature
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*Up to 600 <sup>o</sup>C, temperature ramp rate up to 10 <sup>o</sup>C/s  
*250 <sup>o</sup>C/s
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|style="background:LightGrey; color:black"|Process pressure
|style="background:LightGrey; color:black"|Process pressure
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*1 atm
*1 atm
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|style="background:LightGrey; color:black"|Gasses on the system
|style="background:LightGrey; color:black"|Gases on the system
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*N<sub>2</sub>
*N<sub>2</sub>, max flow 10 SLM
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!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
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*Several smaller samples (placed vertically on a quartz plate)
*Up to 30 4" wafers
*1 6" wafers (placed horizontally on the boat)
*Several smaller samples (placed horizontally on a 6" carrier wafer placed on the boat)
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| style="background:LightGrey; color:black"|Substrate materials allowed
| style="background:LightGrey; color:black"|Substrate materials allowed
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*III-V devices
*Most materials, but samples must be able to tolerate the annealing temperature, and a permission from the Thin Film group is required
*Silicon
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