Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs

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InP etch with HBr chemistry (2019)

Work done by Aurimas Sakanas @Fotonik.dtu 2019. This work was done to obtain very low surface roughness.

Recipe name	?
HBr flow	10 sccm
CH4 flow	5 sccm
Ar flow	2 sccm
Platen power	50 W
Coil power	600 W
Pressure	5 mTorr
Platen chiller temperature	180 oC
Comment	Sample crystal bonded (Crystalbond 509, clear color) to Si carrier

Results
Etch rate	250-350 nm/min (2" wafer) 350-450 nm/min (quarter of a 2" wafer)
Sidewall angle	85-87o (bottom) 93-95o (top) Concave profile
Selectivity (InP:HSQ)	15:1 (2"), 20:1
Other tests	Comparing this recipe with the Cl2/H2 recipe, click here: Media:HBr vs Cl2 InP etch comparison Aurimas.pptx (By Aurimas Sakana @photonic (nov 2019))

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  200 nm wide line structure, t_etch=25 s
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  700 nm wide line structure, t_etch=25 s
  

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  200 nm wide line structure, t_etch=2 min
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  400 nm wide line structure, t_etch=2 min
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  1 µm wide line structure, t_etch=2 min
  

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  Two 1 µm wide line structure, 300 nm gap, t_etch=25 s
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  Two 1 µm wide line structure, 300 nm gap, t_etch=2 min
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  Two 1 µm wide line structure, 500 nm gap, t_etch=2 min
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  Two 1 µm wide line structure, 1 µm gap, t_etch=2 min

InP etch with Cl2/H2 and a Si carrier wafer (2019)

Work done by Berit Herstrøm @Nanolab spring 2019

• Sidewall passivation assisted by a silicon coverplate during and HBr

inductively coupled plasma etching of InP for photonic devices S. Bouchoule, G. Patriarche, S. Guilet, L. Gatilova, L. Largeau, and P. Chabert Citation: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 26, 666 (2008); doi: 10.1116/1.289845

Recipe name	?
Cl2 flow	6.6 sccm
H2 flow	5.4 sccm
Process time	6 min
Platen power	150 W
Coil power	800 W
Pressure	0.5 mTorr (strike pressure 10s@10mTorr)
Platen chiller temperature	180 oC
Comment	Sample placed on a Si carrier

Results
Etch rate	925 nm/min (small piece)
Sidewall angle	90o (on this sample) If you get a small tapered profile try lowering the platen power (to e.g. 100W), this will also decrease the etch rate
Selectivity (InP:SiO2 (PECVD 500nm)	approx.17:1
Other tests made	Comparing of this Cl2/H2 recipe with HBr recipe on e-beamed structures:Media:HBr vs Cl2 InP etch comparison Aurimas.pptx (By Aurimas Sakana @photonic (nov 2019)) A few parameter variations on the recipe, see results on this page!

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InP etch with Cl2/CH4/Ar 2013

Work done by Matthew Haines in 2013

• InP Etch Presentation by Matthew Haines

InP/InGaAsP/InGaAs etch 2011

Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011

Recipe	InP Etch 1/InP Precond 1	?
Cl2 flow	20 sccm	11 sccm
N2 flow	40 sccm	20 sccm
Ar flow	10 sccm	24 sccm
Platen power	100 W	120 W
Coil power	500 W	400 W
Pressure	2 mTorr	2 mTorr
Platen chiller temperature	180 oC	180 oC
Comment	This is for large structures with samll aspect ratio Use SiO2 carrier (not Si) (Kabi/Bghe June 2018)	This is for high aspect ratio

Results (InP Etch 1)
Etch rate	500-600 nm/min
Sidewall angle	86-87 o
Selectivity (InP:SiO2, InP:HSQ)	50:1

• Result of InP etching. David Larsson, DTU Photonics, 2011
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InP etching June 2018

Done by Kabi and Bghe @nanolab

Sample pattern before etching

• Oxide mask before etching.
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  Top view of the SiO2 mask before etching
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  Top view of the SiO2 mask before etching

Etching of an InP piece on Si carrier

InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas.

• Result of InP etching.
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  low roughness in narrow trenched
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  low roughness in narrow trenched
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  A little higher roughnedd is larger trences
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  Much larger roughness in open areas
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  Zoom in on the large roughness
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  closed look at the large roughness in the open areas.

Etching of an InP piece on SiO2 carrier

InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas.

• Result of InP etching.
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  Top view: oxide is gone on the narrow lines, low roughness in the trenches.
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  Top view: low roughness in the trenches.
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  30 dg view: low roughness in the trenches
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  30 dg view: low roughness in the trenches
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  Top view: low roughness in trench and in the large area

Changing the Cl2/N2 ratio

• Result of changing the Cl2/N2 ratio.
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  Sample S0: Top view of the oxide mask before etching. It is the TRAVKA50 mask, but it is clear that the CD reduction is about the 1-1.5 µm of the lines.
• File:None
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  Sample S4: Profile view. The recipe InP etch has been used.
  The sample has been run on a SiO2 carrier wafer.
  There is not much CD change compared to the oxide mask before the etch.
  It seems like the SiO2 mask is gone and the sidewall angle from the mask has been transferred into the sample.
  The sidewall profile is quit vertical in the lower part.
  Etch time 15 min
  Etch depth in large open areas: 9.19µm
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  Sample S5: Profile view. The recipe InP etch has been used but with modified Cl2 and N2 flows: N2=30 sccm Cl2=30 sccm.
  The sample has been run on a SiO2 carrier wafer.
  There is not much CD change compared to the oxide mask before the etch.
  It seems like the SiO2 mask is gone.
  The sidewall profile is overcutting probably due to too little passivation.
  Etch time 10 min
  Etch depth in large open areas: 11.82µm
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  Sample S4: The sidewall roughness on the sample S4 is quite high
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  Sample S5: The sidewall roughness on the sample S5 is quite low.