Specific Process Knowledge/Etch/ICP Metal Etcher: Difference between revisions
New page: ==Etching of nanostructures in silicon using the ICP Metal Etcher== === s === Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches... |
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! rowspan="6" align="center"| Main | ! rowspan="6" align="center"| Main | ||
| Gas | | Gas | ||
| | | HBr 20 sccm | ||
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| Pressure | | Pressure | ||
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| Power | | Power | ||
| | | 900 W CP, 50 W PP | ||
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| Temperature | | Temperature | ||
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| Time | | Time | ||
| | | ? secs | ||
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ER 200 nm/min, 3:1 over resist. Vertical profile. To improve selectivity to oxide under-layers you can add a small amount of O2 ( e.g 2 sccm if the MFC is small enough). This should not give an undercut. | |||
<gallery caption="Standardization images of the shallolr recipe" widths="300px" heights="300px" perrow="2"> | <gallery caption="Standardization images of the shallolr recipe" widths="300px" heights="300px" perrow="2"> |
Revision as of 15:10, 23 February 2011
Etching of nanostructures in silicon using the ICP Metal Etcher
Break | Gas | Cl2 20 sccm |
---|---|---|
Pressure | 2 mTorr, Strike 3 secs @ 5 mTorr | |
Power | 600 W CP, 200 W PP | |
Temperature | 20 degs | |
Hardware | 100 mm Spacers | |
Time | 15 secs | |
Main | Gas | HBr 20 sccm |
Pressure | 2 mTorr, Strike 3 secs @ 5 mTorr | |
Power | 900 W CP, 50 W PP | |
Temperature | 20 degs | |
Hardware | 100 mm Spacers | |
Time | ? secs |
ER 200 nm/min, 3:1 over resist. Vertical profile. To improve selectivity to oxide under-layers you can add a small amount of O2 ( e.g 2 sccm if the MFC is small enough). This should not give an undercut.
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The profile of a 2 m trench
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The profile of a 50 m trench