Specific Process Knowledge/Lithography/EBeamLithography/JEOLAlignment: Difference between revisions
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The job illustrated below writes a chip layout in a 5 x 5 matrix into a 2 x 2 matrix as illustrated in the figure. The first layer, L1, has defined global marks at P = (-30000,0) and Q = (30000,0). The local chip marks are placed at M1 = (-450,450), M2 = (450,450), M3 = (450,-450) and M4=(-450,-450). First a global alignment is called via the '''GLMDET''' command and subsequently chip alignment is called using the '''CHIPAL''' command. The mark positions are stated in the JDF file using the '''GLMPOS''' command for PQ marks and the '''M1''' to '''M4''' commands for chip marks. Remember that a V30 file is placed relative to its bounding box center coordinate and hence it might be necessary to control the bounding box extents by adding control geometry (corner marks) if the design is not symmetric around (0,0) in the chip design coordinate system. | The job illustrated below writes a chip layout in a 5 x 5 matrix into a 2 x 2 matrix as illustrated in the figure. The first layer, L1, has defined global marks at P = (-30000,0) and Q = (30000,0). The local chip marks are placed at M1 = (-450,450), M2 = (450,450), M3 = (450,-450) and M4=(-450,-450). First a global alignment is called via the '''GLMDET''' command and subsequently chip alignment is called using the '''CHIPAL''' command. The mark positions are stated in the JDF file using the '''GLMPOS''' command for PQ marks and the '''M1''' to '''M4''' commands for chip marks. Remember that a V30 file is placed relative to its bounding box center coordinate and hence it might be necessary to control the bounding box extents by adding control geometry (corner marks) if the design is not symmetric around (0,0) in the chip design coordinate system. | ||
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| [[image:EBLChipAlignExample.png|1200px]] | | [[image:EBLChipAlignExample.png|1200px]] | ||
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The following SDF and JDF files will be used for the example. | The following SDF and JDF files will be used for the example. | ||
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