Specific Process Knowledge/Etch/DRIE-Pegasus

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The DRIE Pegasus tools at DTU Nanolab

Unless otherwise stated, all content on this page was created by Jonas Michael-Lindhard, DTU Nanolab

In 2010 DTU Nanolab acquired DRIE-Pegasus 1 (at the time called Danchip and DRIE-Pegasus, respectively). As a state-of-the-art etch tool with excellent performance and great flexibility, it grew immensely popular and by 2015 it was apparent that we needed yet another tool to cope with the demand. Therefore, in 2016 Pegasus 2 was acquired from a closed-down lab in Morocco and installed next to Pegasus 1.

Looking to expand our dry etching capabilities in 2017 we got an irresistible offer on a twin Pegasus system with cassette to cassette vacuum robot from a commerciel fab. The twin Pegasus system (called Pegasus 3 and 4) is installed at the old cluster 2 location in cleanroom C1 and will run only 6" wafers. Pegasus 3 is the 6" silicon etch work horse and Pegasus 4 is converted (adding extra process gases) into a 6" dielectric etch tool that will supplement/replace the AOE.

This page was originally intended as a regular one-machine page (the Pegasus 1 page). However, as of 2018 with several tools, the page will serve as common page for all of our Pegasi with subpages for each tool.

The DRIE-Pegasus 1 load lock and cassette loader in the DTU Nanolab cleanroom A-1. Photo: DTU Nanolab internal	The DRIE-Pegasus 2 operator station and load lock in the DTU Nanolab cleanroom A-1. Photo: DTU Nanolab internal	The DRIE-Pegasus3 and DRIE-Pegasus4 operator station and cassette loading stations. Photo: DTU Nanolab internal

The Bosch process

The DRIE Pegasus tools are state-of-art silicon dry etchers that offer outstanding performance in terms of etch rate, uniformity etc. They use the so-called Bosch process to achieve excellent control of the etched features. Click HERE to access the top of the page. The contents are:

1. Description of the Bosch process
2. Processing options on the Pegasus
3. Modification of the showerhead
4. RF matching
   1. RF matching in general
   2. Why RF matching is extremely important in the Bosch process
5. Picoscope process monitoring

As of 2017, completing the Dry Etch TPT course is mandatory for all new users. On the TPT web page you will find a version of the latest lecture slides - here you will find information as well.

Links to the individual pages for the Pegasi

• DRIE-Pegasus 1
• DRIE-Pegasus 2
• DRIE-Pegasus 3
• DRIE-Pegasus 4

Equipment performance and process related parameters

Equipment		DRIE-Pegasus 1	DRIE-Pegasus 2	DRIE-Pegasus 3	DRIE-Pegasus 4
Purpose	Primary	Dry etching of 4" silicon Dry etching of barc	Research tool	Dry etching of 6" silicon	Dry etching of 6" dielectrics
	Alternative	Black silicon	Backup dry etching of 6" silicon	?	silicon
Performance	Etch rates	Standard processes A and B up to 15 µm/min depending on etch load and feature size Other processes: Any number from 200 nm/min to 10 µm/min	?	?	Depending on the recipe
	Uniformity	For standard processes better than 3 % across a 150 mm wafer.	?	?	Depending on the recipe
Process parameter range	RF powers	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)	Coil Power 5 kW Platen power 300/500 W (HF/LF)
	Gas flows	SF6: 0 to 1200 sccm O2: 0 to 200 sccm C4F8: 0 to 400 sccm Ar: 0 to 283 sccm	SF6: 0 to 1200 sccm O2: 0 to 200 sccm C4F8: 0 to 400 sccm Ar: 0 to 283 sccm	SF6 O2 C4F8 Ar	SF6: 1200 sccm O2: 200 sccm C4F8: 400 sccm Ar: 283 sccm He: 500 sccm CF4: 100 sccm H2: 100 sccm
	Pressure and temperature	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C
	Process options	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps SOI option to reduce notching at buried oxide layers Picoscope monitoring Claritas endpoint detection system	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps SOI option to reduce notching at buried oxide layers Picoscope monitoring Verity OES	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps Picoscope monitoring SOI option to reduce notching at buried oxide layers	Bosch processes with etch and dep cycles each split into three Parameter ramping during process steps Verity OES
Substrates	Sizes	Smaller than 100mm: Bonded to carriers 100 mm wafers: Up to 25 wafers in a batch process	Smaller than 150mm: Bonded to carriers 150 mm wafers	Smaller than 150mm: Bonded to carriers 150 mm wafers	Smaller than 150mm: Bonded to carriers 150 mm wafers
	Loading	Load lock MACS (Multiplex Atmospheric Cassette System)	Load lock	Vacuum cassette loader with two cassette stations and shared dealer chamber with Brooks robot
	Allowed materials	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping
	Possible masking materials	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides Aluminium (only very gentle processes such as process C and nanoetches)	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides Aluminium (only very gentle processes)	AZ and MiR photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides	AZ photoresist zep resist DUV stepper resist (barc + krf) Silicon,Oxides and nitrides Al, Cr masks

Process information

Process notation

Describing a process recipe on the Pegasus may sometimes be difficult because of the great flexibility of the instrument. A compact and precise notation is therefore required for the recipes. Click HERE to find a short description.

Hardware changes

A few hardware modifications have been made on the Pegasus 1 since it was installed in 2010. The changes are listed in the table below under hardware options.

	DRIE-Pegasus 1	DRIE-Pegasus 2	DRIE-Pegasus 3	DRIE-Pegasus 4
Manufactured	2010	2010	2010	2010
Serial	MP0636	MP0641	CP0170	CP0171
Electrode size	4"	6"	6"	6"
Hardware options	High flow plenum Picoscope oscilloscope Claritas optical endpoint system	High flow plenum Picoscope oscilloscope	High flow plenum Picoscope oscilloscope	?

General Pegasus information

Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click HERE.

Characterisation of etched trenches

The trenches in deep silicon trenches can be characterized in many ways. Being able to compare processes requires that a set of common measurements and calculations must be established. Click HERE to find more information about the parameters used on the DRIE-Pegasus process development.

Material from SPTS

• Miscellaneous information