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| Illustration of wafer scale pattern alignment and chip array alignment for two designs, L1 and L2. | | Illustration of wafer scale pattern alignment and chip array alignment for two designs, L1 and L2. |
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| === Boundary box alignment ===
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| In continuation of the example above, if two layers/exposures are to be aligned to each other in subsequent process steps it is vital that the two layers boundary boxes are identical or at least symmetric around (0,0). With reference to the example below, the boundary boxes can be made identical by either
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| *Letting L2 inherit the L1 boundary box (option in Beamer)
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| *Placing small corner marks on L2 to force the boundary box as needed
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| Corner marks can be 1x1 nm boxes placed outside the substrate to avoid having them exposed onto the substrate.
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| [[File:BoundingBoxAlign.png|1000px|center|frameless]]
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| === Detection of alignment mark === | | === Detection of alignment mark === |
