Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions
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== Alignment preparation == | == Alignment preparation == | ||
Alignment on the JEOL 9500 system has a few quirks and pitfalls as a few key elements are not immediately intuitive. The first step to a succesful alignment is proper pattern preparation and understanding how patterns are placed by the system. | |||
===Wafer scale and chip array alignment=== | ===Wafer scale and chip array alignment=== | ||
There is two fundamentally different approaches to pattern alignment on the JEOL 9500 system. One can either do a wafer scale layout where essentially one design covering all elements of the pattern is exposed, i.e. a 1 by 1 array as defined by the ARRAY command. Or, one can expose chips instanced into an array using the ARRAY command. In the first case the pattern can only be aligned via global alignment to a single set of alignment marks defining the wafer coordinate system. In the second case, an initial wafer alignment is made but each chip can then be individually aligned to an extra set of individual chip alignment marks. This is illustrated below. | There is two fundamentally different approaches to pattern alignment on the JEOL 9500 system. One can either do a wafer scale layout where essentially one design covering all elements of the pattern is exposed, i.e. a 1 by 1 array as defined by the ARRAY command. Or, one can expose chips instanced into an array using the ARRAY command. In the first case the pattern can only be aligned via global alignment to a single set of alignment marks defining the wafer coordinate system. In the second case, an initial wafer alignment is made but each chip can then be individually aligned to an extra set of individual chip alignment marks. This is illustrated below. | ||