Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions

There is two fundamentally different approaches to pattern alignment on the JEOL 9500 system. One can either do a wafer scale layout where essentially one design covering all elements of the pattern is exposed, i.e. a 1 by 1 array as defined by the ARRAY command. Or, one can expose chips instanced into an array using the ARRAY command. In the first case the pattern can only be aligned via global alignment to a single set of alignment marks defining the wafer coordinate system. In the second case, an initial wafer alignment is made but each chip can then be individually aligned to an extra set of individual chip alignment marks. This is illustrated below.

In the wafer scale layout, L1 was exposed with a set of global alignment marks (P & Q marks) in order to align the next wafer wide layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design the first exposure of L1 also produced a set of global alignment marks (P & Q marks) but additionally produced a chip alignment mark for each instance of the chip design. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision.