Jump to content

Specific Process Knowledge/Etch/DRIE-Pegasus/processC: Difference between revisions

Jmli (talk | contribs)
Jmli (talk | contribs)
No edit summary
Line 2: Line 2:
<!--Checked for updates on 14/5-2018 - ok/jmli -->
<!--Checked for updates on 14/5-2018 - ok/jmli -->
== Process C ==
== Process C ==
{{Template:Author-jmli1}}
<!--Checked for updates on 2/02-2023 - ok/jmli -->


Process C is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Nanolab wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.
Process C is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Nanolab wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.