Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions

Revision as of 12:02, 31 January 2023 view source Thope (talk \| contribs) DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, NLAB-Nlab347-labadviser-users-35231 2,178 edits →Placement of alignment marks ← Older edit		Revision as of 12:09, 31 January 2023 view source Thope (talk \| contribs) DCH-Employees-701, NLAB-Employees-701, NLAB-LabmanagerAllUsers, NLAB-Nlab347-labadviser-users-35231 2,178 edits →Placement of alignment marks Newer edit →
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	Chip marks should be placed at the corners of each chip with a gap of at least ~~200~~ µm to any important structure. Bear in mind that beam scan during alignment is a high dose exposure of the mark area and hence this resist will develop (for a positive resist). This is illustrated in the microscope images below.		Chip marks should be placed at the corners of each chip with a gap of at least 100 µm to any important structure. Bear in mind that beam scan during alignment is a high dose exposure of the mark area and hence this resist will develop (for a positive resist). This is illustrated in the microscope images below. On the left side is a global mark which has been scanned several times, both in rough scan and fine scan mode. On the right is a chip mark that has been scanned a single time in x and y.

	[[File:9500MarkExposure.png\|1000px\|center\|frameless]]		[[File:9500MarkExposure.png\|1000px\|center\|frameless]]